Yamaha DSP-Z9, Service Manual

Page: 41 / 190

RX-Z9/DSP-Z9
RX-Z9/DSP-Z9
41
2. DSP RAM THROUGH
・Digital PCM 入力の場合は、セレクタ(PLD)設定を
DIAG MODE1 にして DIR 出力をデコーダー(SHARC)
の入力ポート全てに入力される信号経路です。その他は
通常処理で再生します。
・Sp Config は常時無効です。
・各 SRAM の動作チェックは下記のチャンネル出力で判
定します。
SRAM#0....... L/R, C
SRAM#1....... L/R, LFE (SWL/SWR)
SRAM#2....... L/R, SL
SRAM#3....... L/R, SR
SRAM#4....... L/R, SBL
SRAM#5....... L/R, SBR
SRAM#6....... L/R, PL
SRAM#7....... L/R, PR
2. DSP RAM THROUGH
• When using the digital PCM input, this is the signal path
through which the DIR output signals are inputted to all
the input ports of the decoder (SHARC) with the selector
(PLD) set to "DIAG MODE1". With other signal types, they
are reproduced using the ordinary process.
• Sp Config is always invalid.
• The operation of each SRAM is checked by the channel
output as listed below.
SRAM#0....... L/R, C
SRAM#1....... L/R, LFE (SWL/SWR)
SRAM#2....... L/R, SL
SRAM#3....... L/R, SR
SRAM#4....... L/R, SBL
SRAM#5....... L/R, SBR
SRAM#6....... L/R, PL
SRAM#7....... L/R, PR
MIC
DIGITAL
2ch
Analog
8ch
Analog
Pure Direct
L/R L/R
L/R
L/R
SBL/R
SBL/R
SBL/SBR
SBL/SBR
PL/PR
PL/PR
SWL/SWR
SWL/SWR
C/LFE C/LFE
SL/SR
SL/SR
SL/SR
SL/SR
C+/C-
C+/C-
IC14
X3566A0
(DIR)
ADC
CS5361
x 4
i.LINK
MLPCM
i.LINK
DSD
PCB DSP2
IC22
PCB DSP2
YSS930
x 8
DAC
PCM1792 x 6
X3565A0
DECODER DSP
ADSP21161N
X3567A0
4M SRAM
x 8
IC35
IC44
IC70
IC56
IC51
IC64
IC2,
IC4,
IC6,
IC8,
IC10,
IC12,
IC14,
IC16
0dB
0dB
FRONT L/R
+13.0 dBm
CENTER
+13.0 dBm
SURROUND L/R
+13.0 dBm
SUBWOOFER
(50 Hz)
- 16.2 dBm
SPEAKERS OUT (1KHz)
Input level
Both ch, -20 dBm
Volume
+6.5 dB
SURROUND BACK L/R
+13.0 dBm
PRESENCE L/R
+13.0 dBm
INPUT: DVD ANALOG
FULL BIT
・Full bit 出力します。
FULL BIT
• The signals are output in full bit.
FRONT L/R
+13.0 dBm
CENTER
+13.0 dBm
SURROUND L/R
+13.0 dBm
SUBWOOFER
(50 Hz)
- 16.2 dBm
SPEAKERS OUT (1KHz)
Input level
Both ch, -20 dBm
Volume
+6.5 dB
SURROUND BACK L/R
+13.0 dBm
PRESENCE L/R
+13.0 dBm
INPUT: DVD ANALOG
2.RAM THROUGH
0dB
2.RAM THROUGH
FULL BIT