Yamaha DSP-Z9, Service Manual

Page: 133 / 190

A B C D E F G H
1
2
3
4
5
6
I J K L M N
7
8
9
10
133
RX-Z9/DSP-Z9
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
DSP
4M SRAM
AUDIO DECODER DSP
ROM
SDRAM
3.3
3.3
0
0
0
3.3
0
3.3
3.3
0
0
0
0
0
0
0 0 0
0
0 0
0
3.3
3.3 3.3
2.6
2.6
2.6
2.6
2.6
2.6
0
0
0
3.3
3.3
2.6
2.6
2.6 2.6
2.6
2.0
2.6
3.4
3.4
3.4
0
0
0
0
0 0
2.0
3.4
2.6
2.6
2.6
0
0
0 0
3.3
2.6
3.3
3.3 3.3
2.6
2.6
2.6
2.6
0
0
0
0
3.3
3.6
2.6
3.3
3.3
3.3
2.6
2.6
2.6
2.6
0
0
0
0
0
3.3
3.3
0
0
0
3.3
0
3.3
0
0
0
0
0
0
0
0
0
3.3
3.3 3.3
2.6
2.6
2.6
2.6
2.6
2.6
0
0
0
3.3
3.3
2.6
2.6
2.6 2.6 2.6
2.0
2.6
2.6
2.6
0
0
0
0
3.3
2.6
3.3
3.3
3.3
2.6
2.6
2.6
2.6
0
0
0 0
3.3
2.6
3.3
3.3
2.6
2.6
2.6
2.6
0
0
0
0
0 0
0
0
0
4
5
EUROPE
TO DSP1 (1) CB2
Page 131 H-8
TO DSP1 (1) CB3
Page 131 I-8
TO DSP1 (1) CB4
Page 131 J-1
■
SCHEMATIC DIAGRAM (DSP2)
IC29 : 74LCX02MTCX
Quad 2 Input NOR IC30, 31 : SN74LV573APWR
Octal 3-State D-Latcheds
IC20 : SN74AHC2GU04HDCTR
Triple Inverters IC28 : SN74AHC1G32DCKR
Single 2-Input Positive-OR Gate
IC24 : SN74AHC1G08DCKB
2 Input AND Gate
1
2
3
5
4
VDD
OUT X
IN B
VSS
IN A
1A
3Y
GND
VCC
1Y
1
2
3
4 5
2A 3A
2Y
6
7
8 1
2
3 4
5
Y
A
B
GND
VCC
1 2 3 4 5 6 7
Y1 A1 B1 Y2 A2 B2
GND
14 13 12 11 10 9 8
VCC Y4 B4 A4 Y3 B3 A3
IC1, 3, 5, 7, 9, 11, 13, 15 :
CY7C1041CV33-12ZCT
Static RAM
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
INPUT BUFFER
256K x 16
ARRAY
1024 x 4086
R
O
W DECODER
COLUMN
DECODER
SENSE AMPS
A0
A1
A3
A4
A5
A6
A7
A8
A9
A10 A11 A12 A13 A14 A15 A16 A17
I/O0-I/O7
I/O8-I/O15
BHE
WE
CE
OE
BLE
IC23 : MBM29LV160BE-70TN
16M-Bit Flash ROM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
/WE
/RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
/BYTE
VSS
DQ15
DQ17
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
/OE
VSS
/CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RY/BY
RY/BY
BUFFER
ERASE CIRCUIT
WRITE/ERASE
PULSE TIMER
LOW VCC DETECT
VCC
VSS
WE
BYTE
CE
OE
A-1
A0~A18
RESET CONTROL
CIRCUIT
(COMMAND REGISTER)
CHIP ENABLE
OUTPUT ENABLE
CIRCUIT
WRITE CIRCUIT
I/O BUFFER
DQ0~DQ15
DATA LATCH
Y DECODER
X DECODER
ADDRESS LA
TCH
STB
STB
Y GATE
16,777,216
CELL
MATRIX
* All voltages are measured with a 10M
Ω
/V DC electronic volt meter.
* Components having special characteristics are marked
Z
and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
IC27 : W986432DH-7
512K x 4 Banks x 32Bits SDRAM
COLUMN DECODER
CELL ARRY
BANK #0
SENSE AMPLIFIER
ROW DECODER
COLUMN DECODER
CELL ARRY
BANK #1
SENSE AMPLIFIER
ROW DECODER
COLUMN DECODER
CELL ARRY
BANK #3
SENSE AMPLIFIER
ROW DECODER
COLUMN DECODER
CELL ARRY
BANK #2
SENSE AMPLIFIER
ROW DECODER
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
ADDRESS
BUFFER
COLUMN
COUNTER REFRESH
COUNTER
DATA CONTROL
CIRCUIT
DQ
BUFFER
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
BS0
BS1 DMn
DQ0
DQ31
DQM0-3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43 VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VCC
NC
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
DQ24
VSS 86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
IC22 : ADSST-AUDIO7085
DSP Microcomputer
JTAG TEST
AND EMULATION
GPIO
FLAGS
SDRAM
CONTROLLER
EXTERNAL PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
HOST PORT
DMA
CONTROLLER
SERIAL PORTS (4)
LINK PORTS (2)
SPI PORTS (1)
I/O PROCESSOR
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, &
DATA BUFFERS
MULT
MULT
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
ALU ALU
BARREL
SHIFTER BARREL
SHIFTER
BUS
CONNECT
(PX)
DM DATA BUS
PM DATA BUS
DM ADDRESS BUS
PM ADDRESS BUS
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
PROGRAM
SEQUENCER
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR ADDR
ADDR ADDR
DATA
DATA
DATA
DATA
I/O PORT
BLOCK 0
BLOCK 1
IOD
64
IOA
18
8
8
12
24
32
5
16
20
4
32
32
64
64
Output
Control
L
L
L
H
Latch
Enable
H
H
L
X
Data
H
L
X
X
Output
H
L
Q0
Z
OUTPUT
CONTROL
1D
3D
VCC
1Q
1
2
3
4 17
2D 2Q
3Q
18
19
20
4D
5D
4Q
5Q
5
6
7 6D 6Q
16
7D
8D
8
9
10 GND
7Q
8Q
CLOCK
13
15
14
12
11
Q D
>
OE
Q D
>
OE
Q D
>
OE
Q D
>
OE
Q D
>
OE
Q D
>
OE
Q D
>
OE
Q D
>
OE
Point
r
(Pin 3 of IC20)
V : 2V/div, H : 40nsec/div
DC, 1 : 1 probe
0V
Point
t
(Pin 12 of IC22)
V : 2V/div, H : 20nsec/div
DC, 1 : 1 probe
0V