Yamaha dsp-ax3800, Service Manual, Page: 80 / 189

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RX-V3800/DSP-AX3800
RX-V3800/
DSP-AX3800
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53
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55
VSS
AHCLKX0/AHCLKX2
AMUTE0
AMUTE1
AHCLKX1
VSS
ACLKX1
CVDD
ACLKR1
DVDD
AFSX1
AFSR1
VSS
RESET
VSS
CVDD
CLKIN
VSS
TMS
CVDD
TRST
OSCVSS
OSCIN
NC
OSCVDD
VSS
PLLHV
TDI
TDO
VSS
DVDD
EMU[0]
CVDD
EMU[1]
TCK
Ground(Vss)
EM_CAS
EM_WE
EM_WE_DQM[0]
VSS
EM_D[7]
DVDD
EM_D[6]
CVDD
EM_D[5]
EM_D[4]
VSS
EM_D[3]
EM_D[2]
DVDD
EM_D[1]
EM_D[0]
CVDD
VSS
EM_D[15]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PWR
IO
O
PWR
PWR
IO
OZ
IO
IO
IO
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
-
-
-
-
-
-
-
-
-
-
IPU
IPU
-
-
-
-
-
IPU
IPU
IPU
IPU
IPU
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
McASP0 and McASP2 transmit master clock
McASP0 mute output
McASP1 mute output
McASP1 transmit master clock
McASP1 transmit bit clock
McASP1 receive bit clock
McASP1 transmit frame Sync (L/R clock)
McASP1 receive frame Sync (L/R clock)
Device reset pin
Alternate clock input (3.3-V LVCMOS input)
Test mode select
Test reset
Oscillator Vss tap point (for filter only)
1.2-V oscillator input
Oscillator 1.2-V Vpp tap point (for filter only)
PLL 3.3-V supply input (requires external filter)
Test data in
Test data out
Emulation pin 0
Emulation pin 1
Test clock
SDRAM column address strobe
SDRAM write enable
Write enable or byte enable for EM_D [7:0]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
EMIF data bus [lower 16-bits]
NO. Function Name (P.C.B.) TYPE (1) PULL (2) GPIO (3) Detail of Function