Yamaha DP-U50, Service Manual

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DP-U50
DP-U50
23
No. Name I/O Function
1 VSS I GND
2 XI I X'tal in (GND)
3 XO O X'tal out (OPEN)
4 /SIOIRQ O Serial IRQ (OPEN)
5 /FIFOIRQ O FIFO IRQ (/EAINT)
6 A0 I Address Bus
7 A1 I Address Bus
8 A2 I Address Bus
9 A3 I Address Bus
10 A4 I Address Bus
11 A5 I Address Bus
12 TEST9 I (OPEN)
13 TEST10 I (OPEN)
14 D0 I/O Data Bus
15 D1 I/O Data Bus
16 D2 I/O Data Bus
17 D3 I/O Data Bus
18 D4 I/O Data Bus
19 D5 I/O Data Bus
20 D6 I/O Data Bus
21 D7 I/O Data Bus
22 VDD5 I +5V
23 VSS I GND
24 D8 I/O Data Bus
25 D9 I/O Data Bus
26 D10 I/O Data Bus
27 D11 I/O Data Bus
28 D12 I/O Data Bus
29 D13 I/O Data Bus
30 D14 I/O Data Bus
31 D15 I/O Data Bus
32 RDB I Read Strobe input
33 WRL I Write Strobe Low input
34 WRH I Write Strobe High input
35 GACS I Bus Chip Select (EACS)
36 GARST I Global Reset input (USBRST)
37 CPUCLK I System clock input
38 DMVDD I Master Vdd active detection
39 USBDACO O USB audio data
40 CAPTIN I USB capture audio data in (PAO7)
41 TEST0 I OPEN
42 TEST1 I OPEN
43 TEST2 I OPEN
44 VDD5 I +5V
45 VSS I GND
46 MCLKAI I X'tal in (11.2896MHz)
47 MCLKAO O X'tal out (11.2896MHz)
48 PIO0 I/O Extended I/O port (OPEN)
49 PIO1 I/O Extended I/O port (OPEN)
50 PIO2 I/O Extended I/O port (OPEN)
51 PIO3 I YSS928 AC3DATA
52 PIO4 I YSS928 SURENC
53 PIO5 I YSS928 DIRERR
54 PIO6 I YSS928 DIRLOCK
55 PIO7 I YSS928 KARAOKE
IC475 : LC27287B-TF3
Embedded Array
No. Name I/O Function
56 PIO8 I YSS928 OVFB
57 PIO9 I YSS928 DTSDATA
58 PIO10 I YSS928 ZEROFLOG
59 PIO11 I YSS928 CRC
60 PIO12 I/O Extended I/O port (OPEN)
61 PIO13 I YSS928 DBL/V
62 PIO14 I/O Extended I/O port (OPEN)
63 PIO15 I/O Extended I/O port (OPEN)
64 I2CCK O I2C serial Bus clock (OPEN)
65 I2SDA I/O I2C serial Bus data (OPEN)
66 VDD5 I +5V
67 VSS I GND
68 MCLKBI I X'tal in (GND)
69 MCLKBO O X'tal out (OPEN)
70 TEST3 I (OPEN)
71 TEST4 I (OPEN)
72 TEST5 I (OPEN)
73 TEST6 I H: PLL TEST out, L: normal (OPEN)
74 TEST7 I H: pllclks in, L: NC (OPEN)
75 TEST8 I H: PLL TEST out, L: normal (OPEN)
76 PLLCKO I PLL clock input
77 PLLREF O PLL reference clock out
78 RFCLK I Internal PLL reference clock
79 VDD33 I +3.3V
80 PCH O PLL PCH out (TEST8: H) (OPEN)
81 NCH O PLL NCH out (TEST8: H) (OPEN)
82 DIV2 O Internal PLL VCO div2 (OPEN)
83 VSS I GND
84 PO O Charge pomp out
85 VCNT I VCO control input
86 R I VCO Bais Registor
87 AVSS I GND (for Analog)
88 AVDD I +3.3V (for Analog)
89 VSS I GND
90 VDD5 I +5V
91 SFS O Other device audio clock
92 /S64FS O Other device audio clock
93 S128FS O Other device audio clock (OPEN)
94 S256FS O Other device audio clock
95 SSYNC O Other device audio clock (OPEN)
96 R64FS O Render device bit clock (OPEN)
97 C64FS O Capture device bit clock (OPEN)
98 D64FS O USB bit clock (OPEN)
99 S64FS O Other device bit clock (OPEN)
100 X64FS O External bit clock (DIR) (OPEN)
101 XFS I External audio clock (DIR)
102 /X64FS I External audio clock (DIR)
103 X128FS I External audio clock (DIR)
104 X256FS I External audio clock (DIR)
105 XSYNC I External audio clock (DIR)
106 PAI3 I Patch input (A/D)
107 PAI4 I Patch input (YSS928 SDOB0)
108 PAI5 I Patch input (YSS928 SDOB1)
109 PAI6 I Patch input (YSS928 SDOB2)
110 VDD33 I +3.3V