21
CLP-120
■
IC BLOCK DIAGRAM
YMZ702-D (XR632A00) KSN2 (Key Scanner)
PIN
PIN
NO.
NAME
I/O
FUNCTION
NO.
NAME
I/O
FUNCTION
1
BK5
O
21
GND
Ground
2
BK4
O
22
VDD
Power supply
3
BK3
O
Key block (open drein)
23
SO
O
Serial data
4
BK2
O
24
ACK
I
Acknowledge/mode select
5
BK1
O
25
XCK
I
Clock for serial data
6
BK0
O
26
/IC
I
Initial clear
7
MK15
I
27
TST1
I
Test mode
8
MK14
I
28
TST2
I
(L,L: normal mode, others: test)
9
MK13
I
First make contact
29 XCKINH
I
Inhibit of serial clock
10
MK12
I
30
BK14
O
11
MK11
I
31
BK13
O
12
MK10
I
32
BK12
O
13
MK05
I
33
BK11
O
14
MK04
I
34
BK10
O
Key block (open drein)
15
MK03
I
Second make contact
35
BK9
O
16
MK02
I
36
BK8
O
17
MK01
I
37
BK7
O
18
MK00
I
38
BK6
O
19
XIN
I
Crystal osc. input (4 MHz)
39
GND
Ground
20
XOUT
O
Crystal osc. output (4 MHz)
40
VDD
Power supply
3 to 8 Demultiplexer
1
2
3
4
5
6
7
A
A
Select
Enable
Output
Output
B
B
C
C
G2A
G2A
G2B
G2B
G1
G1
Y7
Y7
Y5
Y4
Y3
Y2
Y1
Y0
Y6
16
15
14
13
12
11
10
Vcc
YO
Y1
Y2
Y3
Y4
Y5
8
GND
9
Y6
TC74HC138AFEL (XW762A00)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TD62083F-TPI (XN153A00)
Driver Array
TD62083F-EL (X2550A00)
I1
I2
I3
I4
I5
I6
I7
I8
O1
O2
O3
O4
O5
O6
O7
O8
GND
COMMON
M5227FP (XT773A00)
5-Band Graphic Equalizer
1
2
3
4
5
6
7
IN1
NF1
IN2
NF2
IN3
NF3
IN4
16
15
14
13
12
11
10
-Vcc
GND
+Vcc
OUT
-IN
10k
10k
47k
47k
47k
540
540
540
540
540
540
47k
47k
47k
+IN
NF5
8
NF4
9
IN5
+-
+-
+-
+-
+ -
+ -
PCM69AU-3/TE2 (XV297A00)
DIGITAL-TO-ANALOG CONVERTER
1
2
3
4
5
6
7
19
18
17
16
15
14
20
LV
COM
NC
LI
OUT
SRVCAP
REFCAP
RI
OUT
DCOM
MC2
RDATA
BTCK
SYSCK
WDCK
LDATA
8
NC
MC3
9
12
10
11
13
+V
A
RV
COM
MC1
ACOM
+V
D
SN74C1168NSR (XU073A00)
Line Driver/Receiver
1B
1A
1R
1DE
2R
2A
2B
1D
1Y
1Z
2DE
2Z
2Y
GND
2D
1
2
3
4
5
6
7
8
9
16
15
14
13
12
11
10
TC7S32F(XM588A00)
OR
Vcc
OUT
1
2
3
5
4
IN A
IN B
Vss
