![Yamaha CDR-S1000 Service Manual Download Page 19](http://html.mh-extra.com/html/yamaha/cdr-s1000/cdr-s1000_service-manual_902595019.webp)
CDR-S1000
CDR-S1000
18
IC4 : FHIB31-70A
ACDR
NO.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
PORT
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
VSS
/IC
FSCNT
/IRQ
/WR
/RD
/WAIT
/CS
/DS
PI8
PI7
PI6
PI5
PO9
PO8
PO7
PO6
PO5
PO4
VDD
VSS
DIN
MUTEB
MUTEA
DD0
WC3
BCKO
LRCO
OCLK
VSS
F2561
WC1
F641
SYNC1
EXTW1
DOUTS
DINS
BCKI
LRCI
Name
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
VSS
N_DEV_RST
CDR_FSCNT
N_INT_CDR
N_WR
N_RD
N_CDR_WAIT
N_CDR
N_DS
JG_PIN1
JG_PIN0
DIP3
DIP2
LED2
LED1
DIT_CNTR
SRC_SLW
VDD
VSS
CDR_DIN
MUTEB
MUTEA
CDR_SPD
DIR0_FS
VSS
DIR1_256FS1
DIR1_FS
DIR1_64FS
DIR1_SYNC
EXTW1
DOUTS
DINS
I/O
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
I
I
O
I
I
I
I
I
I
O
O
O
O
O
O
I+
I
I
O
I$
O$T
O$T
O$
I$
I$
I$
I
O$
O
I
O$T
O$T
Function
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface address bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
CPU interface data bus
GND
Initial clear
Fs count signal output
CPU interface interrupt request
CPU interface write strobe
CPU interface read strobe
CPU interface wait
CPU interface chip select
CPU interface data strobe
Extended input port for H8
Extended input port for H8
Extended input port for H8
Extended input port for H8
Extended output port for H8
(N.C.)
Extended output port for H8
(N.C.)
Extended output port for H8
Extended output port for H8
Extended output port for H8
Extended output port for H8
Power supply
GND
Digital audio data input
Digital audio interface output mute
Digital audio interface output mute
Digital audio data output
Word clock input
Bit clock output
(N.C.)
LR clock output
(N.C.)
Clock output
(N.C.)
GND
Clock input (256fs)
Word clock input
Clock input (64fs)
Synchronous signal input
Word clock output (fs)
Serial audio data output
Serial audio data input
Bit clock output
(N.C.)
LR clock output
(N.C.)
DC
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
C
C
T
T
C
T
T
T
T
T
T
C
C
C
C
C
C
T
T
T
C
T
C
C
C
T
T
T
T
C
C
T
C
C