★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
FE RS232 Port
RESET
1.25(1+750/139)=8 (121-9)
(change to +8V)
Capacitor close to IC
KEM-480AAA
RFO+,RFO-,INA,INB,INC,IND signal trace length should <6cm
Close to 8560
LOADER POWER
LOADER CONNECTOR
FE RS232
FAST_EJECT
FEGIO3 LED1
INA
FEFMO2 FMO2
GAINSW3
RFIN
INE
TRINB
FEGIO11 UTXD
INF
TRIND
LDD_SDIO
FEGIO0 MUTE1
FEGIO9 GIO9
TRO
INB
FEFMO
FMO1
GAINSW1
TRINC
TYPWM
RFIN2
FEGIO1 MUTE2
FEFMO4 FMO4
GAINSW2
ING
FOO
INC
TLO
LDD_SEN
RFIP2
TRINA
FEGIO10 URXD
FEDMO
DMO
FEFMO3 FMO3
LDD_CLK
RFIP
INH
IND
FVREF
FPDOCD
FEGIO4 LED2
FEGIO5 GIO5
FEGIO7 GIO7
GIO6
FEGIO6
TRAYOUT#
MPXOUT1
AVDD33_3
MPXOUT2
VWDC2O
MPXOUT3
EJECT#
RSTI
TRAYIN#
VWDC3O
VDAC0
FEFG
FG
AVDD12_2
AVDD12_1
AVDD33_1
FPDODVD
RFO-
RFO+
UTXD
URXD
AUX1
AUX1
VWDC2O
VWDC3O
TRINB
TRINA
TRIND
TRINC
FG
EJECT#
MPXOUT3
MPXOUT1
MPXOUT2
RFIP2
TLO
FOO
TRO
LDD_SEN
LDD_CLK
LDD_SDIO
FPDOCD
GAINSW2
GAINSW1
FMO3
FMO1
TYPWM
FMO4
FMO2
DMO
GAINSW1
GIO7
GIO5
INF
FPDODVD
S80_TILT-
S
LDD_SDIO
RFO-
S80_TR-
ING
AUX1
S
INB
S80_CO_A-
NC
LDD_SEN
INC
RFO+
S80_FR-
HAVC
LDD_CLK
INH
IND
S
S80_CO_B-
INA
INE
TRAYIN#
S80_CO_B-
S
S
S80_TILT-
S80_CO_A-
S80_TR-
S
S80_FR-
FMO1
FMO2
TRAYOUT#
MUTE1
FG
LED2
RFIN2
MUTE2
FEGIO6
FEGIO9
TYPWM
GAINSW3
+12V
S80_VCC_BD_LD
S80_VCC_PDIC
S80_VCC_LD
A3.3V
AVCC
A1.2V
M
M
A1.2V
HAVC
A3.3V
V14REF_T
3.3V
A3.3V
AVCC
VCC
A3.3V
1.2V
3.3V
S80_VCC_LD
S80_VCC_PDIC
S80_VCC_BD_LD
HAVC
VCC
VCC_PS
NETWORK_STBY
1/9, 5/9, 9/9
TRAYIN#
9/9
S
S80_CO_B-
S80_CO_A-
S
S80_TILT-
S
S80_TR-
S80_FR-
FG
9/9
FMO1
9/9
FMO2
9/9
TYPWM#
9/9
TRAYOUT#
9/9
MUTE1
9/9
GIO4
9/9
GAINSW3
9/9
9/9
9/9
9/9
9/9
9/9
9/9
9/9
9/9
9/9
9/9
FB3
BLM18SG121TN1(120/3A/0.025)
MPXOUT1
R137
2K
NC17
NC PAD 0603
DMO
LDD_SDIO
C201
22uF/6.3V/X5R
LDD_CLK
C163
10uF/16V/X5R
TOP
HA3
HEADER 45 SMD0.5 Bottom
JS45P-SMD-L
FR2
1
FD2
2
TD
3
TR
4
FR1
5
FD1
6
GND
7
GND
8
VCC_LDD
9
VCC_LDD
10
GND
11
VCC_LDB
12
VCC_LDB
13
GND
14
GND
15
TEST_V
16
LDEN
17
SEN_LDD
18
SCLK
19
SDIO
20
GND
21
GND
22
NC
23
MODEB
24
MODEA
25
GND_PD
26
RF-
27
RF+
28
GND_PD
29
VCC_PD
30
G
31
A
32
C
33
H
34
F
35
D
36
B
37
E
38
VC_PD
39
THEMO
40
GND
41
SA_B+
42
SA_B-
43
SA_A+
44
SA_A-
45
GND
46
GND
47
GND
48
GND
49
C144
0.1uF/16V/X7R
TLO
C528
4.7uF
TR-
U1F
MT8560-PBGA
V14
H3
FVREF
B4
HAVC
E4
TRINA
A2
TRINB
B3
TRINC
A1
TRIND
B2
INA
C3
INB
B1
INC
C2
IND
C1
INE
E2
INF
E1
ING
D1
INH
D2
FPDODVD
C4
FPDOCD
A3
RFIN
G2
RFIP
G1
RFIP2
H1
RFIN2
H2
FECFREQ
L4
FEOSCEN
K3
FECMOD
L3
FEGAINSW1
L2
FEGAINSW2
M2
FEGAINSW3
L1
FEFMO3
N3
FEFMO4
M3
TLO
J3
TRO
J2
FOO
H4
FETRAYPWM
P2
FEFMO
N1
FEFMO2
N2
FEDMO
P3
FEGIO0
R2
FEGIO1
R3
FEGIO3
U2
FEGIO4
R6
FEGIO5
N5
FEGIO6
N7
FEGIO7
N6
FEGIO9
R5
FEGIO10
T3
FEGIO11
U1
AVDD12_2
J4
AVDD12_1
K5
AGND12_1
H5
AGND12_2
H7
AVDD33_1
E3
AVDD33_3
J6
AGND33_1
F6
AGND33_3
F7
FEFG
R1
AUX1
F5
VDAC0
E5
VWDC3O
A4
VWDC2O
C6
MPXOUT1
F4
MPXOUT2
F2
MPXOUT3
F1
FEEJECT_
T1
FETRAYOUT_
U4
FETRAYIN_
T2
RSTI
E6
AGND33_2
K7
TRINB1
RFIP2
NC14
FMO2
LDD_SEN
C570
0.1uF
C529
0.1uF
TILT-
VWDC3O1
NC26
R145
0/NC
TYPWM
FB5
BLM18SG121TN1(120/3A/0.025)
C522
10uF
R141
2.2K
C142
0.1uF/16V/X7R
VWDC2O1
FR-
FPDOCD
R303
1K/NC
R0603/SMD
C146
0.1uF/16V/X7R
GAINSW1
C521
1uF
C167
0.1uF/50V/X7R
C181
10uF/16V/X5R
TILT+
C143
0.1uF/16V/X7R
C145
0.1uF/16V/X7R
TRINA1
TR+
R306
10K/NC
R0603/SMD
FMO4
C141
2.2uF/10V/X5R
MUTE2
TRINC1
TRIND1
C148
0.1uF/16V/X7R
C170
4.7uF/10V/X5R
GAINSW2
R508
750_1%
C156
NC
C532
10uF
Q300
CES2302/NC
SOT23/SMD
1
3
2
R144
0
C531
0.1uF
C575
0.1uF
C0603/SMD
C140
0.1uF/16V/X7R
TRO
J9
Wafer_2.0_4
1
2
3
4
MPXOUT2
FB4
BLM18SG121TN1(120/3A/0.025)
C159
2.2uF/10V/X5R
R507
140 1%
FMO1
NC15
C204
0.1uF/16V/X7R
C530
0.1uF
FEGIO6
FR+
NC25
FOO
RFIN2
FG1
NC19
C203
22uF/6.3V/X5R
R510
10K
C527
0.1uF
FMO3
C155
10uF/16V/X5R
R143
2.2K/NC
MPXOUT3
C147
0.1uF/16V/X7R
U501
APL1117-ADJ
AD
J/G
N
D
1
OUT
2
IN
3
R1018
0
C533
0.1uF
FEGIO9
R138
4.3K/NC
EJECT#1
2), IC internal pull
down, No need
connect external
pull down resistor.
1), Not allowed to
pull up in circuit
layout:
Signal name
Ball
HW trapping
Note
0: Normal mode (default)
1: Test mode
N6
FEGIO0
FEGIO1
FEGIO6
FEGIO7
FEMPXOUT2
FEMPXOUT1
N7
R3
R2
F2
F4
to BD mechanism unit
Writing port
MAIN 8/9
A
B
C
D
E
F
G
H
I
J
1
2
3
4
5
6
7
38
BD-S677