82
RX-V1
065/HTR-6280/
AX-V1
065
RX-V1065/HTR-6280/AX-V1065
Pin
No.
Port Name
Function
Name
(P.C.B.)
I/O
Detail of Function
P
o
w
er On
Stb
y Thr
h
Standb
y
Stb
y Sleep
Sleep
MCU Sleep
1
TXD4
SCPU_MOSI
SO
O
O
O
O
Synchronous data output for sub-microprocessor
2
CLK4
P95/ANEX0/CLK4
SCPU_SCK
SO
O
O
O
O
Synchronous clock output for sub-microprocessor
3
P94
P94/DA1/TB4in/
CTS4/RTS4/SS4
SCPU_CTS
SI
I
I
O
O
Input for transmission control for sub-microprocessor (clear to send)
4
DA0
P93/DA0/TB3in/
CTS3/RTS3/SS3
AMP_LMT
DA
I
I
I
I
Limiter control output
5
TXD3
P92/TB2in/TXD3/
SDA3/SRXD3/
OUTC20/IEout/
ISTXD2
XM_MOSI
SO
O
O
O
O
Asynchronous data output for XM
(U model)
P92
O
O
O
O
O
(C, R, T, K, A, B, E, F, L, J models)
TB2in
RDS_RDY
TMR
O
O
O
O
RDS RRADY input / Pull-up
(G model)
6
RXD3
P91/TB1in/RXD3/
SCL3/STXD3/IEin/
ISRXD2
XM_MISO
SI
O
O
O
O
Asynchronous data input for XM
(U model)
P91
O
O
O
O
O
(C, R, T, K, A, B, E, F, L, J models)
RXD3
RDS_MISO
SI
O
O
O
O
Synchronous data input for RDS
(G model)
7
P90
P90/TB0in/CLK3
XM_LINK
I
O
O
O
O
XM LINK detection
(U model)
P90
O
O
O
O
O
(C, R, T, K, A, B, E, F, L, J models)
CLK3
RDS_SCK
SO
O
O
O
O
Synchronous clock output for RDS IC / Low level should stand by
(G model)
8
INT8
P146/INT8
IPD_DET
IRQ
IRQ
IRQ
IRQ
O
iPod detection
When inserting an iPod into the DOCK H
→
L
Restriction of port: INT is high edge or low edge only
9
P145
P145/INT7
DIR_N_INT
IRQ
O
O
O
O
DIR interrupt
Restriction of port: INT is high edge or low edge only
10
P144
P144/INT6
DSP_N_INT
IRQ
O
O
O
O
DA70Y interrupt
Restriction of port: INT is high edge or low edge only
11
P143
P143/INPC17/
OUTC17
XM_N_RST
O
O
O
O
O
XM reset
(U model)
P143
O
O
O
O
O
(C, R, T, K, A, B, E, F, L, J models)
RDS_N_RST
O
O
O
O
O
RDS reset
(G model)
12
P142
DIR_SDO
I
O
O
O
O
DIR DATA input at mode of CDDA writing
P142
P142/INPC16/
OUTC16
XM_REV
I
O
O
O
O
XM antenna revision detection
H: An compatibility antenna
(U model)
P142
O
O
O
O
O
(C, R, T, K, A, B, G, E, F, L, J models)
13
P141
P141/INPC15/
OUTC15
DIR_N_CS
CS
O
O
O
O
DIR chip select
14
P140
P140/INPC14/
OUTC14
DSP_N_RST
O
O
O
O
O
DA70Y reset
15
BYTE
BYTE
BYTE
MCU MCU MCU MCU
MCU
Switch of width of data bus input
When set to single chip mode: L (16 bit)
16
CNVss
CNVss
CNVss
MCU MCU MCU MCU
MCU
Processor mode select Low: single chip mode
High: To Flash included boot mode
To boot mode with hardware resetting of P50=H, P55=L, CNVss=H
17
P87
P87/Xcin
DSP_N_CS
CS
O
O
O
O
DA70Y chip select
18
P86
P86/Xcout
DAC_N_CS
CS
O
O
O
O
DAC chip select
19
/RESET
/RESET
/RESET
MCU MCU MCU MCU
MCU Reset
20
Xout
Xout
Xout
MCU MCU MCU MCU
MCU 20 MHz Ceramic resonator
Summary of Contents for AX-V1065
Page 5: ...5 RX V1065 HTR 6280 AX V1065 RX V1065 HTR 6280 AX V1065 AX V1065 J model ...
Page 9: ...9 RX V1065 HTR 6280 AX V1065 RX V1065 HTR 6280 AX V1065 HTR 6280 C model AX V1065 J model ...
Page 162: ...RX V1065 HTR 6280 AX V1065 162 ...
Page 163: ...163 RX V1065 HTR 6280 AX V1065 RX V1065 HTR 6280 AX V1065 ...
Page 164: ...164 RX V1065 HTR 6280 AX V1065 RX V1065 HTR 6280 AX V1065 ...
Page 165: ...165 RX V1065 HTR 6280 AX V1065 RX V1065 HTR 6280 AX V1065 MEMO ...
Page 166: ...RX V1065 HTR 6280 AX V1065 ...
