Yaesu FT-51R, Technical Supplement, Page: 24 / 83

Circuit
VHF PLL Frequency Synthesizer
The VHF PLL circuitry consists of VCO Q4001 and
VCO buffer Q4003 (both
2SC4226)
on the 144 VCO
Unit; PLL subsystem IC Q2007
(FQ7925)
on the 144
Mother Unit, and 12.8-MHz reference oscillator
X3001/Q3009 on the 430 Mother Unit. Q2007 contains
a prescaler, reference divider, serial-to-parallel data
latch, programmable divider, phase comparator,
charge pump, band selector and a power saver cir­
cuit.
While receiving, VCO Q4001 oscillates between
189.05 and 199.05 MHz according to the transceiver
version and the programmed receiving frequency.
The VCO output is buffered by Q4003 and returned
to the 144 Mother Unit, where a sample of that output
is applied to the prescaler section of Q2007. There the
VCO signal is divided by 64 or 65, according to a
control signal from the data latch section of Q2007,
before being applied to the programmable divider
section of Q2007.
The data latch section of Q2007 also receives serial
dividing data from sub-cpu Q1001 on the Control
Unit, which causes the pre-divided VCO signal to be
further divided in the programmable divider section,
depending upon the desired receive frequency, so as
to produce a 5-kHz or 6.25-kHz derivative of the
current VCO frequency. Meanwhile, the reference di­
vider section of Q2007 divides the 12.8-MHz crystal
reference from the 430 Mother Unit, after buffering by
Q3036
(2SC4617),
by 2560 (or 2048) to produce the
5-kHz (or 6.25-kHz) loop reference (respectively).
The 5-kHz (or 6.25-kHz) signal from the program­
mable divider (derived from the VCO) and that de­
rived from the reference oscillator are applied to the
phase detector section of Q2007, which produces a
pulsed output with pulse duration depending on the
phase difference between the input signals. This
pulse train is filtered to DC and returned to varactor
D4001 on the 144 VCO Unit.
Changes in the level of the DC voltage applied to
the varactors affect the reactance in the tank circuit of
the VCO, changing the oscillating frequency of the
VCO according to the phase difference between the
signals derived from the VCO and the crystal refer­
ence oscillator. The VCO is thus phase-locked to the
crystal reference oscillator.
The output of VCO Q4001, after buffering by
Q4002 and Q4003, is delivered to the 144 Mother Unit
for amplification by Q2002 before application to the
1st mixer, as described previously.
For VHF transmission, VCO Q4001 oscillates be­
tween 140 and 150 MHz according to the model ver­
sion and programmed transmit frequency. The
remainder of the PLL circuitry is shared with the
receiver. Howeve1� the dividing data from the micro­
processor is such that the VCO frequency is at the
actual transmit frequency (rather than offset for IFs,
as in the receiving case). Also, the VCO is modulated
by the speech audio applied to D4003, as described
previously. Receive and transmit buses select which
VCO is made active by Q4004
(DTC143ZE).
FET
Q2014
(2SK880GR)
on the 144 Mother Unit buffers
the VCV line for application to the tracking band-pass
filters in the receiver front end.
When the power saving feature is active, the mi­
croprocessor periodically signals the PLL IC to con­
serve power and shorten lock-up time.
UHF PLL Frequency Synthesizer
The UHF PLL circuitry consists of VCO Q5001 and
VCO buffers Q5002 and Q5003 (all
2SC5006)
on the
430 VCO Unit, and PLL subsystem IC Q3009
(FQ7925)
and 12.8-MHz reference oscillator X3001 on
the 430 Mother Unit. Q3009 contains a prescaler, ref­
erence divider, serial-to-parallel data latch, program­
mable divider, phase comparator, band selector and a
power saver circuit.
For receiving, VCO Q5001 oscillates between
488.525 and 508.525 MHz according to model version
and the programmed receiving frequency. A portion
of the VCO output is buffered by Q5003 and returned
to the prescaler section of Q3009 on the 430 Mother
Unit. There the VCO signal is divided by 64 or 65,
according to a control signal from the data latch sec­
tion of Q3009, before being applied to the program­
mable divider section of Q3009.
The data latch section of Q3009 also receives serial
dividing data from sub-cpu Q1001 on the Control
Unit, which causes the pre-divided VCO signal to be
further divided in the programmable divider section,
depending upon the desired receive frequency, so as
to produce a 5-kHz or 6.25-kHz derivative of the
current VCO frequency. Meanwhile, the reference di­
vider section of Q3009 divides the 12.8-MHz crystal
reference by 2560 (or 2048) to produce the 5-kHz (or
6.25-kHz) loop reference (respectively).
The 5-kHz (or 6.25-kHz) signal from the program­
mable divider (derived from the VCO) and that de­
rived from the reference oscillator are applied to the
phase detector section of Q3009, which produces a
dual pulsed output with pulse duration depending
on the phase difference between the input signals.