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XVME-202 Manual
December, 1986

Compatibility . . . . . .

Compatible

with

OPT0 2 2

PAMUX 4 *(or PAMUX 2 if the
PAMUX unit is configured for

8-bit use)

VMEbus Access Time. . . . . . .

Typical

Maximum

DSO ASSERTED TO DTACK ASSERTED (READ)

2500nS

2700nS

DSO ASSERTED TO DTACK ASSERTED (WRITE)

500nS

600nS

DSO NEGATED TO DTACK NEGATED

.

.

65nS

IOOnS

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Summary of Contents for XVME-202

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Page 5: ...to be used as the module base address The module s Internal Registers are accessible at specific addresses offset from the selected module base address 1 2 MANUAL STRUCTURE This manual consists of thr...

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Page 7: ...rees C 32 to 149 degrees F 40 to 85 degrees C 40 to 158 degrees F 5 to 95 RH non condensing Extremely low humidity may require protection against static discharge Sea level to 10 000 ft 3048m Sea leve...

Page 8: ...ith OPT0 2 2 PAMUX 4 or PAMUX 2 if the PAMUX unit is configured for 8 bit use VMEbus Access Time Typical Maximum DSO ASSERTED TO DTACK ASSERTED READ 2500nS 2700nS DSO ASSERTED TO DTACK ASSERTED WRITE...

Page 9: ...AMUX Interface Module are one of the following A A host processor properly installed on the same backplane A properly installed system controller module which provides the following functions Data Tra...

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Page 11: ...MEbus cycles refer to section 2 4 2 of this manual JAl0 JAI5 Select module base address on any one of the 64 1K boundaries within the short I O address space refer to Section 2 4 1 of this manual 2 4...

Page 12: ...OUT I N I N I N I N OUT OUT OUT OUT I N I N I N I N OUT OUT OUT OUT I N I N I N I N OUT OUT OUT OUT I N I N I N I N OUT OUT OUT OUT I N I N I N I N OUT OUT OUT OUT I N I N I N I N OUT 2 4 I N I N OUT...

Page 13: ...UT OUT IN F800H OUT OUT OUT OUT OUT OUT FCOOH 2 4 2 Address Modifier Jumper The XVME 202 has one jumper that determines which Address Modifier Codes it will respond to This jumper is labeled as J2 see...

Page 14: ...rom the XVME 202 to the PAMUX system without the need for a transition interface JKl Pin Signal 1 A0 3 Al 35 5 A2 7 A3 9 A4 11 A5 13 WRITE STROBE 15 READ STROBE 49 RESET Table 2 4 PAMUX in out JKl Pin...

Page 15: ...slowly toward the rear of the chassis until the connectors engage the card should slide freely in the plastic guides 4 Apply straight f orward pressure to of the module until the connector is fully e...

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Page 17: ...he ribbon does not exceed 500 feet 2 8 OPTIONAL ON BOARD OSCILLATOR Jumper Jl is used to select between the VMEbus signal SYSCLK or an optional 16 MHz oscillator Position JIB selects the VMEbus SYSCLK...

Page 18: ...handle 9 on the 3U front panel By removing the screw nut found inside the handle the entire handle assembly will separate from the 3U front panel Remove the counter sunk screw 8 to separate the 3U fr...

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Page 20: ...sses may be used with the understanding that only the odd byte of the word is used to exchange PAMUX data The PAMUX data bus is only 8 bits wide while the PAMUX unit contains 32 points of I O To be ab...

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Page 23: ...hed to write to bank 12 When the user is writing to a relay bank that has input and output modules the user MUST make sure that zeros are written to the input module positions If the user write s a 1...

Page 24: ...RRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress INTERRUP...

Page 25: ...e that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driv...

Page 26: ...iven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word transfe...

Page 27: ...n INTERRUPT REQUEST 1 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indi...

Page 28: ...tor driven signal which when low will cause the system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high le...

Page 29: ...A Row B Signal Signal Mnemonic Mnemonic D00 BBSY D O 1 BCLR DO2 ACFAIL DO3 BGOIN DO4 BGOOUT DO5 BGlIN DO6 BGlOUT DO7 BG2IN GND BG20UT SYSCLK BG3IN GND BG3OUT DSI BRO DSO BRl WRITE BR2 GND BR3 DTACK AM...

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