Xycom Xembedded XPMC-6710, Reference Manual

Page: 13 / 36

Overview
Document Number: 646710 13
Monarch vs. Non-Monarch
There are Two types of Processor PMCs as defined by the American National Standard for
Processor PMC (ANSI/VITA 32-2003), a master or host and slave or target. The XPMC-6710
is a Monarch type Processor PMC. While generally understood, these definitions can become
confusing, especially since the clock generator and PCI arbiter reside on the Processor PMC
carrier. With hopes of minimizing confusion with other architectures and definitions, the terms
monarch and non-monarch will be used in this document. The monarch is defined as the main
PCI bus Processor PMC (or CPU); the one that performs PCI bus enumeration after power-up
and may be an interrupt handler. A Non-monarch is therefore not the main CPU, does not
perform PCI bus enumeration after power-up and may be an interrupt generator. The
MONARCH signal defines a Processor PMC as a being a monarch or a non-monarch.
Naturally there shall only be one monarch per system while there can be as many
non-monarchs as the electrical interface on the carrier will support. The optional EREADY
signal is an output of non-monarch Processor PMCs that indicates it has completed its
on-board initialization and can respond to PCI bus enumeration by the monarch via
configuration cycles. The term “Host” is used in the PMC/CMC standard to define the
motherboard or carrier to which a PMC or Processor PMC is attached. To further minimize
confusion, throughout the remainder of this document, the term “carrier” will be used when
referring to that board.