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XJTAG-XCFM-Guide-22K-02.1
www.xjtag.com
XJLink2-CFM .
User Guide
5. Powering the Board
The XJLink2-CFM is powered from the Teradyne MFAB connector J12 using pins 8, 10, 12, and 14.
6. Configuring XJLink2-CFM Interface Voltages
The 18 interface pins on the XJLink2-CFM are divided into two banks of nine. Each bank can operate at a
different voltage level.
Setting the Bank Voltages
The voltage domain used for each bank can be set in software, either by selecting a standard logic level or
by defining a custom voltage in the Advanced Settings. The input and output voltage levels can be set
independently.
As an alternative to setting the bank voltages in software, the bank voltage can be made to mirror an
external value. This is done by configuring a pin in software to have type VREF, VREF1, or VREF2 and
applying a voltage to that pin. The bank voltage will then be set to match the applied voltage. Each bank
can have its own Vref source. For details of how to use a common reference voltage source for both
banks or two individual ones, refer to the Help System’s XJLink2 section.
Interface Logic Voltage Characteristics
By default, the logic levels on the interface will be determined by the selected bank voltage. If standard
logic levels are chosen, the voltage characteristics will be as shown in Table 4.
Table 4 – Interface Logic Voltage Characteristics
If a custom level is defined for the logic voltages, or the bank voltages are set using a Vref input, the user
should refer to the XJTAG Help system for details of the logic thresholds that will apply.
Bank Voltage
VIL max
VIH min
VOL max
VOL min
Load conditions
3.3
0.8
2
0.4
2.4
100
Ω
2.5
0.7
1.7
0.4
2
100
Ω
1.8
0.4
0.9
0.4
1.35
100
Ω
1.5
0.4
0.85
0.4
1
100
Ω
1.2
0.4
0.75
0.4
0.8
133
Ω
Input voltage
7 – 18 V, nominal 12 V
Current
500 mA max.
Bank 1
XJLink pins 1 – 9
Bank 2
XJLink pins 11 – 19
Output voltage range
1.1 V to 3.5 V in 0.1 V steps
Output voltage tolerance
±5%, typically ±3%