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Xilinx XC4000E Series, Manual

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Xilinx XC4000E Series Manual Download Page 43

March 30, 1998 (Version 1.5)

4-43

A18 - A21

(XC4000X

only)

O

I/O

During Master Parallel configuration with an XC4000X master, these 4 output pins add
4 more bits to address the configuration EPROM. After configuration, they are user-pro-
grammable I/O pins. (See Master Parallel Configuration section for additional details.)

D0 - D7

I

I/O

During Master Parallel and Peripheral configuration, these eight input pins receive con-
figuration data. After configuration, they are user-programmable I/O pins.

DIN

I

I/O

During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.

DOUT

O

I/O

During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DIN input.
In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.

Unrestricted User-Programmable I/O Pins

I/O

Weak

Pull-up

I/O

These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (25 k

Ω

 - 100 k

Ω

) that defines the logic level as High.

Table 17: Pin Descriptions (Continued)

Pin Name

I/O

During

Config.

I/O

After

Config.

Pin Description

Summary of Contents for XC4000E Series

Page 1: ...Control Signals 4 11 Using FPGA Flip Flops and Latches 4 11 Using Function Generators as RAM 4 11 Fast Carry Logic 4 18 Input Output Blocks IOBs 4 21 IOB Input Signals 4 21 IOB Output Signals 4 24 Ot...

Page 2: ...55 Configuration Through the Boundary Scan Pins 4 55 Readback 4 56 Readback Options 4 57 Read Capture 4 57 Read Abort 4 57 Clock Select 4 57 Violating the Maximum High and Low Time Specification for t...

Page 3: ...ts 4 92 XC4000EX Pin to Pin Input Parameter Guidelines 4 93 XC4000EX Global Early Clock Set Up and Hold for IFF 4 93 XC4000EX Global Early Clock Set Up and Hold for FCL 4 93 XC4000EX Input Threshold A...

Page 4: ...Pin Locations for XC4025E XC4028EX XL Devices 4 125 Pin Locations for XC4036EX XL 4 128 Pin Locations for XC4044XL Devices 4 131 Pin Locations for XC4052XL Devices 4 135 Pin Locations for XC4062XL De...

Page 5: ...imization Low Voltage Versions Available Low Voltage Devices Function at 3 0 3 6 Volts XC4000XL High Performance Low Voltage Versions of XC4000EX devices Additional XC4000X Series Features Highest Per...

Page 6: ...programmed devices Taking Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system This capability gives the sys tem designer a new degree o...

Page 7: ...carry chain through a single CLB TBYP have improved by as much as 50 from XC4000 values See Fast Carry Logic on page 4 18 for more information Select RAM Memory Edge Triggered Synchronous RAM Modes Th...

Page 8: ...in XC4000X Only Increased Routing New interconnect in the XC4000X includes twenty two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs The twelve Q...

Page 9: ...e function generator outputs However the stor age elements and function generators can also be used independently These storage elements can be configured as flip flops in both XC4000E and XC4000X dev...

Page 10: ...ible for each storage element Any inverter placed on the clock input is automatically absorbed into the CLB Clock Enable The clock enable signal EC is active High The EC pin is shared by both storage...

Page 11: ...own in Figure 2 A two to one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs This bypass is sometimes used by the automated router t...

Page 12: ...s Edge Triggered Synchronous data written by the designated edge of the CLB clock WE acts as a true clock enable Level Sensitive Asynchronous an external WE signal acts as the write strobe The selecte...

Page 13: ...ps between CLB pins and RAM inputs and outputs for single port edge triggered mode are shown in Table 6 The Write Clock input WCLK can be configured as active on either the rising edge default or the...

Page 14: ...ITE PULSE LATCH ENABLE LATCH ENABLE K CLOCK WE D1 D0 EC WRITE PULSE MUX 4 4 Figure 5 16x2 or 16x1 Edge Triggered Single Port RAM G 4 G1 G4 F1 F4 C1 C4 WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY X6754 4...

Page 15: ...ive Timing Mode Note Edge triggered mode is recommended for all new designs Level sensitive mode also called asynchronous mode is still supported for XC4000 Series backward com patibility with the XC4...

Page 16: ...contents are defined via an INIT attribute or property attached to the RAM or ROM symbol as described in the schematic library guide If not defined all RAM contents are initialized to all zeros by def...

Page 17: ...ED AH T X6462 Figure 9 Level Sensitive RAM Write Timing Enable G 4 G1 G4 F1 F4 WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY X6746 4 READ ADDRESS MUX Enable F WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY 4 REA...

Page 18: ...hain in XC4000E devices can run either up or down At the top and bottom of the columns where there are no CLBs above or below the carry is propagated to the right See Figure 12 In order to improve spe...

Page 19: ...4000X devices when the minor logic changes are taken into account The fast carry logic can be accessed by placing special library symbols or by using Xilinx Relationally Placed Mac ros RPMs that alrea...

Page 20: ...1998 Version 1 5 D Q S R EC YQ Y DIN H G F G H D Q S R EC XQ DIN H G F H X H F G G4 G3 G2 G1 F F3 F2 F1 F4 F CARRY G CARRY C C DOWN CARRY LOGIC D C C UP K S R EC H1 X6699 OUT IN OUT IN IN COUT0 Figur...

Page 21: ...iggered flip flop or a level sensitive latch The choice is made by placing the appropriate library sym bol For example IFD is the basic input flip flop rising edge triggered and ILD is the basic input...

Page 22: ...Buffer Passive Pull Up Pull Down 2 I1 X6704 Figure 16 Simplified Block Diagram of XC4000E IOB Q Flip Flop Latch Fast Capture Latch D Q Latch D G D 0 1 CE CE Q Out T Output Clock I Input Clock Clock E...

Page 23: ...e hold time requirement Sufficient delay eliminates the possibility of a data hold time requirement at the external pin The maxi mum delay is therefore inserted as the default The XC4000E IOB has a on...

Page 24: ...al Early buffer and clocks the Fast Capture latch appropriately Figure 17 on page 4 22 also shows a two tap delay on the input By default if the Fast Capture latch is used the Xilinx software assumes...

Page 25: ...de and more than 5 ns dura tion This level of ground bounce may cause undesired transient behavior on an output or in the internal logic This restriction is common to all high speed digital ICs and is...

Page 26: ...se sensitivity The configurable pull up resistor is a p channel transistor that pulls to Vcc The configurable pull down resistor is an n channel transis tor that pulls to Ground The value of these res...

Page 27: ...8 Three State Buffer Modes The 3 state buffers can be configured in three modes Standard 3 state buffer Wired AND with input on the I pin Wired OR AND Standard 3 State Buffer All three pins are used P...

Page 28: ...ey can be combined with other logic to form a PAL like AND OR struc ture The decoder outputs can also be routed directly to the chip outputs For fastest speed the output should be on the same chip edg...

Page 29: ...cks Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew Global routing can also be used for other high fanout signal...

Page 30: ...length lines associated with each CLB These lines connect the switch ing matrices that are located in every row and a column of CLBs Single length lines are connected by way of the program mable switc...

Page 31: ...G LE D O U BLE LO N G G LO BAL QUAD LONG SINGLE DOUBLE LONG LO N G DOUBLE D O U BLE Q U AD G LO BAL Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix CLB D IR EC T FEED BAC K DIREC...

Page 32: ...ndent inputs and up to two independent outputs Only one of the inde pendent inputs can be buffered The place and route software automatically uses the timing requirements of the design to determine wh...

Page 33: ...terconnect delays I O Routing XC4000 Series devices have additional routing around the IOB ring This routing is called a VersaRing The VersaRing facilitates pin swapping and redesign without affecting...

Page 34: ...l Quad Single Double Long Direct Connect Long INTERCONNECT IOB WED WED WED IOB Figure 32 High Level Routing Diagram of XC4000 Series VersaRing Left Edge WED Wide Edge Decoder IOB I O Block shaded arro...

Page 35: ...C T A L E D G E D E C O D E QUAD LONG SINGLE DOUBLE LONG L O N G DOUBLE D O U B L E G L O B A L IK OK I1 CE I2 T O DECODER DECODER Common to XC4000E and XC4000X XC4000X only IOB IOB DIRECT Figure 34...

Page 36: ...y Global buffers offer the shortest delay and negligible skew Four Secondary Global buffers have slightly longer delay and slightly more skew due to poten tially heavier loading but offer greater flex...

Page 37: ...n X4 4 IOB CLOCKS CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN locals locals locals locals locals BUFGLS locals BUFGLS BUFGLS BUFGLS BUFGLS BUFGE BUFGE BUFGE...

Page 38: ...pe in parallel This configuration is particu larly useful when using the Fast Capture latches as described in IOB Input Signals on page 4 21 Paired Glo bal Early and Global Low Skew buffers share a co...

Page 39: ...g expla nation Each Global Early buffer can access the eight vertical Glo bal lines for all CLBs in the quadrant Therefore only one fourth of the CLB clock pins can be accessed This restric tion is in...

Page 40: ...onditions may be capable of driving sinking up to 10 times as much current under best case conditions Noise can be reduced by minimizing external load capaci tance and reducing simultaneous output tra...

Page 41: ...o Vcc User I O Pins That Can Have Special Functions RDY BUSY O I O During Peripheral mode configuration this pin indicates when it is appropriate to write another byte of data into the FPGA The same s...

Page 42: ...l global net with short delay and minimal skew If not used to drive a global buffer any of these pins is a user pro grammable I O The PGCK1 PGCK4 pins drive the four Primary Global Buffers Any input p...

Page 43: ...nfiguration DIN is a user programmable I O pin DOUT O I O During configuration in any mode but Express mode DOUT is the serial configuration data output that can drive the DIN of daisy chained slave F...

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