Xilinx XC4000E Series, Manual

Page: 16 / 43

XC4000E and XC4000X Series Field Programmable Gate Arrays
4-16 March 30, 1998 (Version 1.5)
Figure 9 shows the write timing for level-sensitive, single-
port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 8 .
Figure 10 and Figure 11 show block diagrams of a CLB
configured as 16x2 and 32x1 level-sensitive, single-port
RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 8: Single-Port Level-Sensitive RAM Signals
G'
G1 • • • G4
F1 • • • F4
WRITE
DECODER
1 of 16
D
IN
16-LATCH
ARRAY
X6748
4
4
MUX
F'
WRITE
DECODER
1 of 16
D
IN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WRITE PULSE
MUX
4 4
C1 • • • C4
4
WE D1 D0
EC
Figure 8: 16x1 Edge-Triggered Dual-Port RAM
RAM Signal CLB Pin Function
D D0 or D1 Data In
A[3:0] F1-F4 or G1-G4 Address
WE WE Write Enable
O F’ or G’ Data Out