MP3 NG: A Next Generation Consumer Platform
XAPP169 (v1.0) November 24, 1999
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The only software support required for this block is the screen BIOS which consists of functions
to generate screen images by manipulating the frame buffer memory. This buffer appears as an
array of 512, 32-bit words with each word containing 32 pixels of the screen image. The most
significant bit of the word at the base address appears as the pixel in the upper left-hand corner
of the screen. The least significant bit of that memory word appears as the 32
nd
pixel in the first
row. The word and bit address of any pixel on the screen can be calculated using the following
formula:
Memory Interface
The memory interface block,
Figure 18
implements the data path required to map the 8- and
16-bit memory devices to the 32-bit IP bus. While the RC32364 is capable of fetching instruc-
tions and data from devices with varying bus widths, having the FPGA build 32-bit words for the
CPU reduces the number of bus cycles. This increases performance and also reduces power
consumption.
Figure 16 on page 16
shows a block diagram of this block.
Memory Address
Bit Address
= X * Y MOD 32
= X * Y REM 32
Where:
X and Y are the horizontal and vertical coordinates of the screen and
assume that the origin (X = 0, Y = 0) is in the upper left-hand corner of the screen.
MOD the integer division.
REM is the remainder of the division
MUX
MUX
D_IN[7:0]
D_IN[15:8]
D_IN[23:16]
D_IN[31:24]
MEM_DOUT[15:8]
MEM_DOUT[7:0]
MEM_D[15:0]
Register
Q
D
MUX
D_OUT[31:24]
Register
Q
D
D_OUT[23:16]
Register
Q
D
MUX
D_OUT[15:8]
D_OUT[7:0]
MEM_DIN[15:8]
MEM_DIN[7:0]
MUX
MEM_ADDR[10:0]
A_IN[8:1]
A_IN[19:9]
A_IN[10:0]
Figure 18: Memory Interface Block Diagram
