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Usage Model

When FEC is enabled in 50G mode, bit 0 of each TXDATA bus must be the first bit to be
transmitted in time, and bit 159 must be the last bit to be transmitted in time. The
TXDATASTART signal must be driven High whenever the TXDATA for the associated channel
contains the first 160 bits of a codeword. Input codewords must always be aligned so that bit 0
of a codeword is on bit 0 of the TXDATA bus.

When FEC is enabled in 100G mode, bit 0 of CH0_TXDATA must be the first bit to be
transmitted in time, and bit 159 of CH1_TXDATA must be the last bit to be transmitted in time.
The CH0_TXDATASTART signal must be driven High whenever the TXDATA buses contain the
first 320 bits of a codeword. Input codewords must always be aligned so that bit 0 of a codeword
is on bit 0 of CH0_TXDATA. CH1_TXDATASTART is ignored in 100G mode.

In all modes, codewords are 5440 bits in length. The final 300 bits of data is reserved for the
insertion of FEC parity. At the input to the FEC, bits 5140 to 5439 of the input data must be set
to 0.

50G Ethernet

Up to two channels of 50G Ethernet with KP4 FEC can be implemented as per IEEE Draft
Standard for Ethernet Amendment: Media Access Control Parameters for 50 Gb/s and Physical Layers
and Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operation (IEEE Std 802.3cd
Clause 134). Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
pre-FEC PCS data rate is 51.5625 Gb/s, and the nominal post-FEC line rate is 53.125 Gb/s.

100G Ethernet

One channel of 100G Ethernet with KP4 FEC can be implemented as per IEEE Std 802.3-2015
Clause 91. Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
aggregate pre-FEC PCS data rate is 103.125 Gb/s and the nominal aggregate post-FEC line rate
is 106.25 Gb/s.

100G OTN FlexO

One channel of 100G OTN FlexO with a KP4 FEC can be implemented as per ITU-T G.709.1,
Flexible OTN Short-Reach Interface. Transcoding should be disabled in the GTM Wizard IP for this
mode. The nominal aggregate post-FEC line rate is 111.81 Gb/s.

100G Interlaken

One channel of 100G Interlaken with KP4 FEC can be implemented as per the Interlaken Reed-
Solomon Forward Error Correction Extension Protocol Definition. Transcoding should be disabled in
the GTM Wizard IP for this mode. Line rates up to 58 Gb/s are possible.

Chapter 3: Transmitter

UG581 (v1.0) January 4, 2019

Virtex Ult GTM Transceivers

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Summary of Contents for Virtex UltraScale+ FPGAs

Page 1: ...Virtex UltraScale FPGAs GTM Transceivers User Guide UG581 v1 0 January 4 2019...

Page 2: ...ble shows the revision history for this document Section Revision Summary 01 04 2019 Version 1 0 Initial Xilinx release N A Revision History UG581 v1 0 January 4 2019 www xilinx com Virtex UltraScale...

Page 3: ...lection and Distribution 14 LCPLL 18 Reset and Initialization 23 Power Down 45 Loopback 46 Dynamic Reconfiguration Port 47 Digital Monitor 50 Chapter 3 Transmitter 54 TX Interface 55 TX FEC 63 TX Buff...

Page 4: ...Interface 123 AC Coupled Reference Clock 124 Unused Reference Clocks 125 Reference Clock Output Buffer 125 Reference Clock Power 125 Power Supply and Filtering 125 PCB Design Checklist 129 Appendix A...

Page 5: ...ignal processing bandwidth as well as the highest on chip memory density As the industry s most capable FPGA family the Virtex UltraScale devices are ideal for applications including 1 Tb s networking...

Page 6: ...e UltraScale architecture GTM transceivers and is part of the UltraScale architecture documentation suite available at www xilinx com ultrascale Features The GTM transceiver in the UltraScale FPGA is...

Page 7: ...50GE LAUI 50GE LAUI2 Ethernet AN LT auto negotiation link training OTU4 Interlaken at 53 125 Gb s 25 78125 Gb s and 12 5 Gb s CPRI at 48 Gb s 24 Gb s 12 Gb s and 10 1 Gb s The first time user is recom...

Page 8: ...s Contrary to other UltraScale device transceivers such as the GTH and GTY transceivers the GTM transceiver does not contain channel common primitives All channel ports and attributes are within the G...

Page 9: ...TM Transceivers Wizard The UltraScale FPGAs GTM Transceivers Wizard hereinafter called the Wizard is the preferred tool to generate a wrapper to instantiate the GTM_DUAL The Wizard is located in the I...

Page 10: ...mixed language simulator is required The simulator must be able to simulate VHDL and Verilog simultaneously An installed GTM transceiver SecureIP model The correct setup of the simulator for SecureIP...

Page 11: ...C file templates that configure the transceivers and contain placeholders for GTM transceiver placement information The XDC files generated by the Wizard can then be edited to customize operating para...

Page 12: ...nt location The mode of operation cannot be changed during run time Input Mode The reference clock input mode structure is illustrated in the following figure The input is terminated internally with 5...

Page 13: ...e HROW routing Refer to Reference Clock Selection and Distribution for more details The following table defines the attributes in the IBUFDS_GTM software primitive that configure the reference clock i...

Page 14: ...clock output port that gets mapped to GTREFCLKN The following table defines the attributes in the OBUFDS_GTM software primitive that configure the reference clock output Table 6 Reference Clock Output...

Page 15: ...clude Clock routing for northbound and southbound clocks Flexible clock inputs available for the LCPLL Static or dynamic selection of the reference clock for the LCPLL The Dual architecture has two GT...

Page 16: ..._GTM output O to the GTREFCLK ports of GTM_DUAL Figure 7 Single External Reference Clock in a Dual GTM_DUAL GTREFCLK MGTREFCLKP MGTREFCLKN I IB IBUFDS_GTM O X20898 061418 Note The IBUFDS_GTM diagram i...

Page 17: ...pin pair MGTREFCLKP MGTREFCLKN must not exceed three Duals The maximum number of Duals that can be sourced by a single clock pin pair is three six transceivers Designs with more than three Duals requi...

Page 18: ...t is reserved for internal testing purposes only GTREFCLK In Clock External clock driven by IBUFDS_GTM for the LCPLL GTNORTHREFCLK In Clock Northbound clock from the Dual below GTSOUTHREFCLK In Clock...

Page 19: ...t is fed into the phase frequency detector The feedback divider N determines the voltage controlled oscillator VCO multiplication ratio For line rates below 28 1 Gb s NRZ and 56 2 Gb s PAM4 a fraction...

Page 20: ...3 and Equation 2 4 show how to determine the fractional divider presented in Equation 2 1 FractionalDivider NSDM 0 FractionalPart FractionalPart SDMDATA 2SDMWIDTH The table below lists the allowable v...

Page 21: ...CLKLOST ports It does not affect the LCPLL lock detection reset and power down functions PLLPD In Async An active High signal powers down the LCPLL PLLREFCLKLOST Out PLLMONCLK A High on this signal in...

Page 22: ...d CRS_CTRL_CFG1 16 bit Reserved Use the recommended value from the Wizard DRPEN_CFG 16 bit Reserved Use the recommended value from the Wizard PLL_CFG0 16 bit Reserved Use the recommended value from th...

Page 23: ...e Wizard Reset and Initialization The GTM transceiver must be initialized after device power up and configuration before it can be used The GTM transmitter TX and receiver RX can be initialized indepe...

Page 24: ...port for the GTM transceiver TX GTRXRESET is the initialization reset port for the GTM transceiver RX During initialization reset TXRESETMODE and RXRESETMODE should be set to sequential mode All TX P...

Page 25: ...dependently for a predetermined time set by its attribute It does not process any state after the requested state as shown in Figure 13 for the GTM transceiver TX or Figure 18 for the GTM transceiver...

Page 26: ...dth is one period of the reference clock After a PLLRESET pulse the internal reset controller generates an internal LCPLL reset followed by an internal SDM reset The time required for LCPLL to lock is...

Page 27: ...needed sequential mode allows you to reset the TX from activating TXPMARESET and continue the reset state machine until TXRESETDONE transitions from Low to High The TX reset state machine does not re...

Page 28: ...cates TX PMA reset is complete CH 0 1 _TXRESETDONE Out TXUSRCLK This active High signal indicates the GTM transceiver TX has finished reset and is ready for use This port is driven Low when GTTXRESET...

Page 29: ...G1 16 bit Reserved Bit Name Address Description TX_FEC_RESET_TIME 4 0 Represents the time duration to apply a TX CKCAL reset Use the recommended value from the Wizard Must be a non zero value when TXP...

Page 30: ...owing figure RECOMMENDED Use the associated PLLLOCK from the PLL to release GTTXRESET from High to Low as shown in the figure The TX reset state machine waits when GTTXRESET is detected High and start...

Page 31: ...ts are toggled in sequence depending on TXPMARESTMASK and TXPCSRESETMASK selection When TXRESETMODE is set to single mode the internal resets are toggled simultaneously depending on TXPMARESETMASK and...

Page 32: ...Recommended TX Reset Setting TXRESETMODE TXPMARESETMASK TXPCSRESETMASK1 After power up and configuration PLL Entire TX 2 b00 2 b11 2 b11 After turning on a reference clock to the PLL being used PLL E...

Page 33: ...s or the GTM transceiver s are powered up after configuration perform a full TX sequential reset after the PLL fully completes its reset procedure After Changing the Reference Clock to the PLL being U...

Page 34: ...ered sequentially The reset state machine executes the reset sequence as shown in the following figure covering the entire RX PMA and RX PCS During normal operation the reset state machine runs until...

Page 35: ...No RXRESETDONE High RXPMARESETMASK 4 1 RX Adapt Reset Yes No RXPMARESETMASK 5 1 RX CDR PH Reset Yes No RXPMARESETMASK 6 1 RX CDR FR Reset Yes No RXPCSRESETMASK 0 1 RX Eye Scan Reset Yes No RXPCSRESET...

Page 36: ...Bit 1 ADC CLKGEN Bit 0 RX PMA Top CH 0 1 _RXPCSRESETMASK 3 0 In Async RX PCS reset mask selection Bit 3 PRBS counter Bit 2 RX PCS top Bit 1 FEC Bit 0 Eye Scan CH 0 1 _RXUSERRDY In Async This port is d...

Page 37: ...RESET In Async This port is driven High and then deasserted to start a single mode reset on DSP The reset is not dependent on RXRESETMODE or RXPMARESETMASK setting CH 0 1 _RXEYESCANRESET In Async This...

Page 38: ...n RX ADC CLKGEN reset Use the recommended value from the Wizard Must be a non zero value when RXPMARESETMASK 1 is High and GTRXRESET initiates the reset process CH 0 1 _RST_TIME_CFG3 16 bit Reserved U...

Page 39: ...Bit Name Bit Field Description RX_PRBS_RESET_TIME 4 0 Reserved Represents the time duration to apply a PRBS counter reset Use the recommended value from the Wizard Must be a non zero value when RXPCS...

Page 40: ...7 4 Reserved Use the recommended value from the Wizard RX_PMA_LOOPER_START_ID 3 0 Reserved Use the recommended value from the Wizard CH 0 1 _RST_LP_CFG4 16 bit Reserved Use the recommended value from...

Page 41: ...ion GTM Transceiver RX Reset in Response to GTRXRESET Pulse in Full Sequential Mode The GTM transceiver allows you to reset the entire RX at any time by sending GTRXRESET an active High pulse These co...

Page 42: ...re available to perform single resets of the respective RX components When direct single reset ports are toggled a single reset is performed regardless of RXPMARESETMASK RXPCSRESETMASK and RXRESETMODE...

Page 43: ...erence Clock to the PLL Being Used If the reference clock s changes or GTM transceiver s are powered up after configuration perform a full RX sequential reset after the PLL fully completes its reset p...

Page 44: ...can lock to incoming data After Recovered Clock Becomes Stable Depending on the design of the clocking scheme it is possible for the RX reset sequence to be completed before the CDR is locked to the i...

Page 45: ...Name Address Description RX_PDB_CH0 2 This active Low signal powers down channel 0 RX RX_PDB_CH1 3 This active Low signal powers down channel 1 RX PLL Power Down To activate the LCPLL power down mode...

Page 46: ...igure 21 Loopback Testing Overview RX PMA RX PCS TX PMA TX PCS RX PCS RX PMA RX PMA TX PCS TX PMA Near End GTM Transceiver Far End GTM Transceiver Link Near End Test Structures Link Far End Test Struc...

Page 47: ...01 Reserved 3 b110 Far End PCS Loopback The following table defines the loopback attributes Table 24 Loopback Attributes Attribute Type Description CH 0 1 _TX_LPBK_CFG0 16 bit Reserved Use the recomme...

Page 48: ...DY assertion depends on the relationship between the DRPCLK frequency and the USRCLK frequency For read only registers if a DRPRDY is not seen within 500 DRPCLK cycles after initiating a DRP transacti...

Page 49: ...wing figure shows the DRP read operation timing New DRP operations can be initiated when DRPY is asserted Figure 23 DRP Read Timing DRPCLK DRPEN DRPRDY DRPWE DRPADDR DRPDI DRPDO ADR DAT X20219 052318...

Page 50: ...tor Ports Port Dir Clock Domain Description CH 0 1 _DMONITOROUT 31 0 Out Async Local Clock Digital monitor output bus for channel 0 1 CH 0 1 _DMONITORCLK In Async Channel 0 1 digital monitor clock CH...

Page 51: ...0 1 _RX_APT_CFG12B 16 bit Reserved Bit Name Bit Field Description TESTSEL 15 Must be set to 1 b0 when reading adaptation loops in channel 0 1 CH 0 1 _RX_APT_CFG18A 16 bit Reserved Bit Name Bit Field...

Page 52: ...10 4 b1110 FFE tap hp11 Use Mode Reading loop values out of Digital Monitor requires a clock on input port CH0 1_DMONITORCLK change adaptation loop select through DRP and monitor output CH0 1_DMONITOR...

Page 53: ...DMON_SRC 0x233 14 12 DEMONCON 0x23B 15 TESTSEL 0x246 15 12 DFELOOPSEL 0x23f 15 12 FFELOOPSEL Chapter 2 Shared Features UG581 v1 0 January 4 2019 www xilinx com Virtex UltraScale GTM Transceivers 53 Se...

Page 54: ...l data Figure 24 GTM Transceiver TX Block Diagram Pattern Generator Polarity FIFO To RX Parallel Data Near End PCS Loopback From RX Parallel Data Far End PCS Loopback TX Interface FEC Gray Encoder Pre...

Page 55: ...ath in PAM4 mode that is configurable by setting the TX_INT_DATA_WIDTH attribute When the FEC is enabled only the 80 bit internal datapath may be used The interface width is configurable by setting th...

Page 56: ...itter The required rate for TXUSRCLK depends on the internal datapath width of the GTM_DUAL primitive and the TX line rate of the GTM transmitter The following equation shows how to calculate the requ...

Page 57: ...erved for TXUSRCLK and TXUSRCLK2 TXUSRCLK and TXUSRCLK2 must be positive edge aligned with as little skew as possible between them As a result low skew clock resources BUFG_GTs must be used to drive T...

Page 58: ...bit fabric width 64 bit internal datapath must be used with 64 or 128 bit fabric width 0x0 64 bit internal datapath mode 0x1 80 bit internal datapath mode 0x2 128 bit internal datapath mode GEN_TXUSR...

Page 59: ...Bit Mode In the following figure TXPROGDIVCLK is used to drive TXUSRCLK and TXUSRCLK2 in 64 bit 80 bit or 128 bit mode in a single lane configuration In all cases the frequency of TXUSRCLK2 is equal t...

Page 60: ...LK and TXUSRCLK2 64 Bit 80 Bit or 128 Bit Mode Design in UltraScale Architecture UltraScale Devices GTM Transceiver TXPROGDIVCLK BUFG_GT1 TXUSRCLK22 TXUSRCLK2 3 TXDATA TX data width 64 80 128 bits Ult...

Page 61: ...6 bits 2 BUFG_GT1 X20913 111918 Notes relevant to the figure 1 For details about placement constraints and restrictions on clocking resources such as BUFG_GT and BUFG_GT_SYNC refer to the UltraScale A...

Page 62: ...GT1 UltraScale Devices GTM Transceiver TXDATA TX data width 128 160 256 bits TXUSRCLK22 TXUSRCLK2 X20918 111918 Notes relevant to the figure 1 For details about placement constraints and restrictions...

Page 63: ...PN scrambling for backplane operations The general principle of operation of the FEC is the same whichever mode is chosen When RS FEC is enabled in the transmit direction data to be FEC encoded and tr...

Page 64: ...RCLK and CH1_TXUSRCLK2 inputs can be tied to ground The following table shows the TX FEC related attributes for the GTM dual Table 33 TX FEC Attributes Attribute Type Description FEC_CFG0 16 bit Reser...

Page 65: ...EE Draft Standard for Ethernet Amendment Media Access Control Parameters for 50 Gb s and Physical Layers and Management Parameters for 50 Gb s 100 Gb s and 200 Gb s Operation IEEE Std 802 3cd Clause 1...

Page 66: ...y Encoder TX PCS PISO TX Driver TX Pre Pre 2 Post Emp TX PMA TX Interface TX Serial Clock PMA Parallel Clock XCLK PCS Parallel Clock TXUSRCLK Device Parallel Clock TXUSRCLK2 X20914 053018 Pre Coder Th...

Page 67: ...ress 0x689 Note This is a read only attribute CH 0 1 _TXFIFO_OVERFLOW 1 bit A value of 1 indicates FIFO overflow For channel 0 bit 9 of DRP address 0x489 For channel 1 bit 9 of DRP address 0x689 Note...

Page 68: ...d PRBS test pattern for 10 Gigabit Ethernet See IEEE Std 802 3ae 2002 IMPORTANT For PAM4 modulation QPRBS patterns are supported by sending a conventional PRBS pattern with PAM4 and Gray Coding based...

Page 69: ...01 PRBS 7 4 b0010 PRBS 9 4 b0011 PRBS 15 4 b0100 PRBS 23 4 b0101 PRBS 31 4 b0110 PRBS 13 4 b1000 Reserved 4 b1001 Alternating 1b 0 and 1 b1 4 b1010 Square wave with 64 UI period CH 0 1 _TXPRBSINERR In...

Page 70: ...dress 0x083 for CH0 0x283 for CH1 a CH 0 1 _TX_PCS_CFG0 4 0 0x12 for 80 bit data width mode b CH 0 1 _TX_PCS_CFG0 4 0 0x14 for 160 bit data width mode 2 Enable the PRBS generator by setting CH 0 1 _TX...

Page 71: ...CH0_TXUSRCLK2 The CH0_TXPOLARITY port is used to invert the polarity of the outgoing data for channel 0 0 Not inverted TXP is positive and TXN is negative 1 Inverted TXP is negative and TXN is positi...

Page 72: ...In PAM4 mode this attribute enables Gray encoding In NRZ mode the default Wizard value must be used 1 b0 Enables Gray encoding 1 b1 Disables Gray encoding IMPORTANT In PAM4 mode if Gray encoder is ena...

Page 73: ...this attribute enables pre coding In NRZ mode the default Wizard value must be used 1 b0 Enables pre code 1 b1 Disables pre code IMPORTANT In PAM4 mode if pre coder is enabled for the transmitter the...

Page 74: ..._TXPROGDIVCLK is used as the source of the interconnect logic clock via BUFG_GT 2 There is only one LCPLL in the GTM_DUAL primitive which is shared between the TX RX TX Programmable Divider The TX pr...

Page 75: ...1 _TXPROGDIVCLK Out Clock TXPROGDIVCLK is the parallel clock output from the TX programmable divider This clock is the recommended output to the interconnect logic through BUFG_GT Table 44 TX Program...

Page 76: ...10 32 64 6 b100110 40 80 6 b001101 48 96 6 b100111 50 100 6 b101101 60 120 6 b001110 64 128 6 b001111 80 160 6 b101111 100 200 When the following settings are set TX_PROGDIV_SEL_DIV66 1 b0 TX_PROGDIV_...

Page 77: ..._TXOUTCLKSEL 2 0 In Async This port must be set to 3 b000 CH 0 1 _TXOUTCLK Out Clock Reserved CH 0 1 _TXPROGDIVCLK Out Clock TXPROGDIVCLK is the parallel output clock from the TX programmable divider...

Page 78: ...s and Attributes The following table defines the TX configurable driver ports Table 46 TX Configurable Driver Ports Port Dir Clock Domain Description CH 0 1 _TXDRVAMP 4 0 Input Async Driver swing cont...

Page 79: ...5 b00000 and CH 0 1 _TXEMPPRE2 4 b0000 2 For UltraScale FPGAs the output swing described above is obtained using settings from the Wizard design and the recommended values from the Wizard should not...

Page 80: ...001 3 7 2 3 9 5 b01010 4 2 2 6 10 5 b01011 4 8 2 9 11 5 b01100 5 4 3 2 12 5 b01101 6 0 3 5 13 5 b01110 6 7 3 9 14 5 b01111 7 5 4 2 15 5 b10000 8 3 4 6 16 5 b10001 9 2 5 0 17 5 b10010 N A 5 4 18 5 b100...

Page 81: ...0 0 0 4 b0001 0 3 0 2 1 4 b0010 0 7 0 5 2 4 b0011 1 1 0 7 3 4 b0100 1 5 0 9 4 4 b0101 1 9 1 2 5 4 b0110 2 3 1 5 6 4 b0111 2 7 1 7 7 4 b1000 N A 2 0 8 4 b1001 N A 2 3 9 4 b1010 N A 2 6 10 4 b1011 N A...

Page 82: ...8 19 5 b10100 N A 6 2 20 5 b10101 N A 6 7 21 5 b10110 N A 7 2 22 5 b10111 N A 7 7 23 5 b11000 N A 8 3 24 5 b11001 N A 8 9 25 5 b11010 N A 9 2 26 Notes 1 The peak to peak differential voltage is defin...

Page 83: ...r 1 b0 The CH 0 1 _TXEMPMAIN coefficient is automatically determined 1 b1 CH 0 1 _TXEMPMAIN coefficient can be independently set by the CH 0 1 _TXEMPMAIN pins within the range specified in the pin des...

Page 84: ...gic Figure 36 GTM Transciever RX Block Diagram Polarity FIFO PRBS Checker RX Interface FEC Gray Encoder Pre Coder RX PCS DFE FFE RX EQ SIPO ADC RX PMA To RX Parallel Data Near End PCS Loopback From RX...

Page 85: ...OM_MODE PAD_RTERM_VCOM_LVL X20922 111918 Ports and Attributes The following table defines the RX AFE ports Table 48 RX AFE ports Ports Dir Clock Domain Description CH 0 1 _GTMRXP CH 0 1 _GTMRXN In Pad...

Page 86: ...e Address Description PAD_RTERM_VCOM_MODE 12 11 Controls the mode for the RX termination voltage 2 b00 AVTT 2 b01 Reserved 2 b10 Floating 2 b11 Programmable PAD_RTERM_VCOM_LVL 10 7 Controls the common...

Page 87: ...transmission media and receiver The transmission media of the channel is bandwidth limited and the signal traveling through is subjected to attenuation and distortion The GTM receiver is an ADC based...

Page 88: ...E or RXPMARESETMASK setting CH 0 1 _RXADCCALRESET In Async Reserved Tie to 1 b0 CH 0 1 _RXADCCLKGENRESET In Async This port is driven High and then deasserted to start a single mode reset on the RX AD...

Page 89: ...loop KH adapt value 10 Enable to freeze current CTLE Low frequency loop KL adapt value 9 Enable to freeze current Offset Cancelation OS adapt value 8 5 Reserved 4 Enable to freeze current FFE Tap HM4...

Page 90: ...o freeze current FFE Tap HP8 adapt value 5 Enable to freeze current FFE Tap HP7 adapt value 4 Enable to freeze current FFE Tap HP6 adapt value 3 Enable to freeze current FFE Tap HP5 adapt value 2 Enab...

Page 91: ...Cancelation OS value according to attribute CH 0 1 _RX_APT_CFG17B 6 0 8 5 Reserved 4 Enable to override FFE Tap HM4 value according to attribute CH 0 1 _RX_APT_CFG14B 5 0 3 Enable to override FFE Tap...

Page 92: ...ng to attribute CH 0 1 _RX_APT_CFG13B 5 0 2 Enable to override FFE Tap HP4 value according to attribute CH 0 1 _RX_APT_CFG13B 12 6 1 Enable to override FFE Tap HP3 value according to attribute CH 0 1...

Page 93: ...mpled The sampled data then moves through FFE and DFE before feeding to the CDR state machine and the downstream transceiver blocks The LCPLL provides a base clock to the phase interpolator The phase...

Page 94: ...from the Wizard CH 0 1 _RX_CDR_CFG1B 16 bit CDR configuration Use the recommended value from the Wizard CH 0 1 _RX_CDR_CFG2A 16 bit CDR configuration Use the recommended value from the Wizard CH 0 1 _...

Page 95: ...1 CH 0 1 _RXPROGDIVCLK is used as the source of the interconnect logic clock via BUFG_GT 2 There is only one LCPLL in the GTM_DUAL primitive which is shared between the TX RX 3 RXRECCLK 0 1 is the sa...

Page 96: ...cription CH 0 1 _RX_ANA_CFG1 16 bit Reserved Bit Name Address Description RX_PROGDIV_SELFR 13 This attribute is used during the RX programmable divider ratio selection Set to 1 b1 to obtain the full r...

Page 97: ...6 b100010 20 40 6 b000101 24 48 6 b100011 25 50 6 b100101 30 60 6 b000110 32 64 6 b100110 40 80 6 b001101 48 96 6 b100111 50 100 6 b101101 60 120 6 b001110 64 128 6 b001111 80 160 6 b101111 100 200 W...

Page 98: ...s poses a challenge to system bring up because the quality of the link cannot be determined by measuring the far end eye opening at the receiver pins At high line rates the received eye measurement on...

Page 99: ...16 bit Reserved Bit Name Address Description RX_PRECODE_ENDIAN 11 In PAM4 mode this attribute controls pre coder received endianness In NRZ mode the default Wizard value must be used 1 b0 Non invertin...

Page 100: ...mode if the Gray Encoder is enabled for the receiver the transmitter Gray Encoder should also be enabled for proper data recovery RX Polarity Control If the RXP and RXN differential traces are acciden...

Page 101: ...ronizing and works on the incoming data before comma alignment or decoding This function can be used to test the signal integrity of the channel Figure 43 RX Pattern Checker Block Polarity Control SIP...

Page 102: ...5 cycles after reset After being asserted High CH 0 1 _RXPRBSLOCKED does not deassert until reset of the RX pattern checker via a reset of the RX GTRXRESET RXPMARESET or RXPCSRESET in sequential mode...

Page 103: ...data The counter increments by the actual number of bit errors Counting begins after RXPRBSLOCKED is asserted High The counter saturates at 32 hFFFFFFFF This error counter can only be accessed via th...

Page 104: ...83 for CH0 0x283 for CH1 a CH 0 1 _RX_PCS_CFG0 4 0 0x09 for 80 bit data width mode b CH 0 1 _RX_PCS_CFG0 4 0 0x0B for 160 bit data width mode 3 Set CH 0 1 _RXPMARESETMASK 0x0 4 Toggle CH 0 1 _GTRXRESE...

Page 105: ...es phase compensation between the two clocks The RX buffer inside the GTM transceiver must always be used Buffer bypass is not allowed Table 63 RX FIFO Data Width Conversion Scenarios PMA Parallel Clo...

Page 106: ...d on the RS 544 514 code which encodes message blocks of 5140 bits to produce codewords of 5440 bits For a detailed description of the RS FEC sublayer in Ethernet including the definition of the KP4 F...

Page 107: ...CLK2 Output RX data Must use 160 bit interface when FEC is enabled CH 0 1 _RXDATASTART Out CH 0 1 _RXUSRCLK2 Start of codeword CH 0 1 _RXDATAISAM Out CH 0 1 _RXUSRCLK2 Alignment marker flag CH 0 1 _RX...

Page 108: ...ol error count increment FECRXLN3ERRCNTINC 3 0 Out CH1_RXUSRCLK2 Lane 3 symbol error count increment FECRXLN0MAPPING 1 0 Out CH0_RXUSRCLK2 Logical FEC lane mapped to physical lane 0 FECRXLN1MAPPING 1...

Page 109: ...Attributes Attribute Type Description FEC_CFG0 16 bit Reserved Bit Name Address Description FEC_RX0_MODE 11 8 Operation mode for FEC RX slice 0 4 b0000 FEC is disabled for this channel 4 b0001 50G KP4...

Page 110: ...RX_VL_MARKER_ID1 31 16 FEC_CFG10 15 0 FEC_RX_VL_MARKER_ID1 47 32 FEC_CFG11 15 0 FEC_RX_VL_MARKER_ID1 63 48 64 bit Binary Alignment marker 0 common for 50GE operation on FEC RX slice 1 Ignored if FEC R...

Page 111: ...oneous data is not flagged until after it has been output Usage Model When FEC is enabled in 50G mode bit 0 of each RXDATA bus is the first bit received in time and bit 159 is the last bit received in...

Page 112: ...One channel of 100G OTN FlexO with a KP4 FEC can be implemented as per ITU T G 709 1 Flexible OTN Short Reach Interface Transcoding should be disabled in the GTM Wizard IP for this mode The nominal a...

Page 113: ...nal datapath in PAM4 mode that is configurable by setting the TX_INT_DATA_WIDTH attribute When the FEC is enabled only the 80 bit internal datapath can be used The interface width is configurable by s...

Page 114: ...tter The required rate for RXUSRCLK depends on the internal datapath width of the GTM_DUAL primitive and the RX line rate of the GTM transmitter The following equation shows how to calculate the requi...

Page 115: ...RXUSRCLK2 must be positive edge aligned with as little skew as possible between them As a result low skew clock resources BUFG_GTs must be used to drive RXUSRCLK and RXUSRCLK2 If the channel is config...

Page 116: ...bit internal datapath must use with 128 or 256 bit fabric width 64 bit internal datapath must use with 64 or 128 bit fabric width 0x0 64 bit internal datapath mode 0x1 80 bit internal datapath mode 0...

Page 117: ...re the differential output pairs for each of the transceivers in the GTM transceiver Dual MGTAVTTRCAL In Pad Bias current supply for the termination resistor calibration circuit See Termination Resist...

Page 118: ...the location of the power supply group for a specific GTM transceiver Dual The nominal voltage is 0 9 VDC or 0 85 VDC depending on the speed grade See the UltraScale device data sheets see http www xi...

Page 119: ...hnology devices each slice to be used that contains multiple Duals must be powered on Connect the MGTAVTTRCAL pin to the MGTAVTT supply and to a pin on the 100 precision external resistor The other pi...

Page 120: ...If a PSG does not have an RCAL master and it is powered all the PSGs on that side left or right of the package must be powered If a PSG with an RCAL master is unpowered any PSGs without an RCAL master...

Page 121: ...lation shown in Figure 50 as used in the GTM transceiver portion of the UltraScale device data sheets see http www xilinx com documentation Figure 49 Single Ended Clock Input Voltage Swing Peak to Pea...

Page 122: ...s Figure 52 GTM Transceiver Board Design Guidelines MGTREFCLKP 50 50 UltraScale FPGAs MGTAVCC MGTREFCLKN REFCLK to GTM Transceiver Dedicated Clock Routing X21023 060718 GTM Transceiver Reference Clock...

Page 123: ...on the differential transmission lines to a minimum impedance discontinuities generate jitter Reference Clock Interface LVDS The following figure shows how an LVDS oscillator is connected to a refere...

Page 124: ...www xilinx com documentation AC Coupled Reference Clock AC coupling of the oscillator reference clock output to the GTM transceiver Dual reference clock inputs serves multiple purposes Blocking a DC c...

Page 125: ...lock from this circuit Power Supply and Filtering The GTM transceiver Dual requires three analog power supplies MGTAVCC at a nominal voltage level of 0 85 VDC or 0 9 VDC for UltraScale FPGAs MGTVCCAUX...

Page 126: ...erating state of the GTM transceiver goes from power up to power down the load current transient is negative and the voltage from the regulator might spike while the regulator circuit adapts to the ne...

Page 127: ...rs require an input voltage that is higher than the output voltage This minimum dropout voltage often is dependent on the load current Even low dropout linear regulators require a minimum difference b...

Page 128: ...upply regulation circuit requires a switching transistor element an inductor and a capacitor Depending on the required efficiency and load requirements a switching regulator circuit might require exte...

Page 129: ...sign Checklist The following table is a checklist of items that can be used to design and review any GTM transceiver PCB schematic and layout Table 74 GTM Transceiver PCB Design Checklist Pins Recomme...

Page 130: ...nF Transmitter data traces should be provided enough clearance to eliminate crosstalk from adjacent signals If a transmitter is not used leave the associated pin pair unconnected MGTAVTTRCAL Connect...

Page 131: ...sumption refer to the Xilinx Power Estimator XPE at www xilinx com power MGTMAVTT N 1 For UltraScale FPGAs the nominal voltage is 1 2 VDC See the UltraScale device data sheets see http www xilinx com...

Page 132: ...ce data sheets see http www xilinx com documentation for power supply voltage tolerances The power supply regulator for this voltage should not be shared with non transceiver loads Many packages have...

Page 133: ...x004 15 0 R W CH0_TX_ANA_CFG1 15 0 0 65535 0 65535 0x005 15 0 R W CH0_TX_ANA_CFG2 15 0 0 65535 0 65535 0x006 15 0 R W CH0_TX_ANA_CFG3 15 0 0 65535 0 65535 0x007 15 0 R W CH0_TX_DRV_CFG3 15 0 0 65535 0...

Page 134: ...0 65535 0x025 15 0 R W CH0_RX_APT_CFG1B 15 0 0 65535 0 65535 0x026 15 0 R W CH0_RX_APT_CFG2A 15 0 0 65535 0 65535 0x027 15 0 R W CH0_RX_APT_CFG2B 15 0 0 65535 0 65535 0x028 15 0 R W CH0_RX_APT_CFG3A 1...

Page 135: ...65535 0x04a 15 0 R W CH0_RX_APT_CFG20A 15 0 0 65535 0 65535 0x04b 15 0 R W CH0_RX_APT_CFG20B 15 0 0 65535 0 65535 0x04c 15 0 R W CH0_RX_APT_CFG21A 15 0 0 65535 0 65535 0x04d 15 0 R W CH0_RX_APT_CFG21B...

Page 136: ...535 0 65535 0x085 15 0 R W CH0_TX_PCS_CFG2 15 0 0 65535 0 65535 0x086 15 0 R W CH0_TX_PCS_CFG3 15 0 0 65535 0 65535 0x087 15 0 R W CH0_TX_PCS_CFG4 15 0 0 65535 0 65535 0x088 15 0 R W CH0_TX_PCS_CFG5 1...

Page 137: ...35 0 65535 0x0ad 15 0 R W CH0_RST_LP_CFG4 15 0 0 65535 0 65535 0x0ae 15 0 R W RST_CFG 15 0 0 65535 0 65535 0x0af 15 0 R W RST_PLL_CFG0 15 0 0 65535 0 65535 0x0b0 15 0 R W PLL_CFG0 15 0 0 65535 0 65535...

Page 138: ...35 0 65535 0x0e0 15 0 R W FEC_CFG16 15 0 0 65535 0 65535 0x0e1 15 0 R W FEC_CFG17 15 0 0 65535 0 65535 0x0e2 15 0 R W FEC_CFG18 15 0 0 65535 0 65535 0x0e3 15 0 R W FEC_CFG19 15 0 0 65535 0 65535 0x0e4...

Page 139: ...15 0 R W CH1_RX_PAD_CFG0 15 0 0 65535 0 65535 0x213 15 0 R W CH1_RX_PAD_CFG1 15 0 0 65535 0 65535 0x214 15 0 R W CH1_RX_CDR_CFG4A 15 0 0 65535 0 65535 0x215 15 0 R W CH1_RX_CDR_CFG4B 15 0 0 65535 0 6...

Page 140: ...7 15 0 R W CH1_RX_APT_CFG10B 15 0 0 65535 0 65535 0x238 15 0 R W CH1_RX_APT_CFG11A 15 0 0 65535 0 65535 0x239 15 0 R W CH1_RX_APT_CFG11B 15 0 0 65535 0 65535 0x23a 15 0 R W CH1_RX_APT_CFG12A 15 0 0 65...

Page 141: ...0 0 65535 0 65535 0x25c 15 0 R W CH1_RX_DSP_CFG 15 0 0 65535 0 65535 0x264 15 0 R W CH1_RX_CAL_CFG2A 15 0 0 65535 0 65535 0x265 15 0 R W CH1_RX_CAL_CFG2B 15 0 0 65535 0 65535 0x267 15 0 R W CH1_RX_CA...

Page 142: ..._CH_CFG1 15 0 0 65535 0 65535 0x297 15 0 R W CH1_A_CH_CFG2 15 0 0 65535 0 65535 0x298 15 0 R W CH1_A_CH_CFG3 15 0 0 65535 0 65535 0x299 15 0 R W CH1_A_CH_CFG4 15 0 0 65535 0 65535 0x29a 15 0 R W CH1_A...

Page 143: ...umentation and Tutorials On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design...

Page 144: ...e viewed at https www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be f...

Page 145: ...nd other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Appendix B Additional Reso...

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