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Xilinx Virtex-II Pro ML324, User Manual

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Xilinx Virtex-II Pro ML324 User Manual Download Page 22

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www.xilinx.com

Virtex-II Pro ML324 and ML325 Platform

UG063 (v1.2)  May 30, 2006

Detailed Description

R

19. RS-232 Port Pins 

The RS-232 port pins are as shown in 

Table 17

. The pins are set up in DTE mode as shown 

in 

Figure 3

.

Table 17:

R

S

-232 Port Pins

FPGA UART

Port Name

Direction

Net

ML324

ML325

TXD

OUT

T1IN

AK25

AV34

RTS

OUT

T2IN

AP26

AU34

RXD

IN

R1OUT

AR26

AR34

CTS

IN

R2OUT

AM25

AT34

Figure 3:

R

S

-232 Pins in DTE Mode

UG063_03_042506

RS-232

DB9

Virtex-II Pro

U1

U2

J52

T1IN

TXD

RTS

RXD

CTS

Pin 3

Pin 7

Pin 2

Pin 8

T2IN

R1OUT

R2OUT

Summary of Contents for Virtex-II Pro ML324

Page 1: ...R Virtex II Pro ML324 and ML325 Platform User Guide UG063 v1 2 May 30 2006 P N 0402276 03...

Page 2: ...WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO...

Page 3: ...itch 11 2 Power Supply Jacks 12 3 FPGA Configuration 12 4 Oscillator Sockets 13 5 Single Ended SMA Clocks 13 6 Differential Oscillators 14 7 Differential SMA Clock 14 8 User LEDs Active High 15 9 User...

Page 4: ...4 www xilinx com Virtex II Pro ML324 and ML325 Platform UG063 v1 2 May 30 2006 R...

Page 5: ...h the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support Conventions This document uses the...

Page 6: ...design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has...

Page 7: ...for System ACE solution RS 232 cable Power supply CD ROM Contents User guide in PDF format Example design file for demonstration of the RocketIO transceivers System ACE files ace for each part type su...

Page 8: ...capable of supplying 3A each Power supply jacks for optional use of external power supplies JTAG configuration port for use with Parallel Cable III and Parallel Cable IV cables System ACE configurati...

Page 9: ...ANGLE SMA RIGHT ANGLE SMA RIGHT ANGLE SMA PROGRAM MGT MGT System ACE Solution UART RX TX DONE LED INIT LED LEDs GP SWs PB SW 1 PB SW 2 Power Bus and Switches 5V Jack 5V Brick or VCC Jack VCCO Jack AU...

Page 10: ...ption The ML325 platform show in n Figure 2 represents the ML32x platforms described in this user guide Each feature is detailed in the numbered sections that follow Figure 2 Detailed Description of V...

Page 11: ...These can be used to deliver a fixed voltage by appropriate selection of the resistors designated as R32 R39 R46 and R49 default is set to 2 5V These can be made to deliver a variable voltage by depo...

Page 12: ...transceivers on the top and bottom edges of the FPGA VT_TX top set and bottom set VT_RX top set and bottom set Note 5V must always be applied to the 5V jack or to the external power brick connector t...

Page 13: ...ators and are powered by 3 3V or the VCCO 2 5V power supply 5 Single Ended SMA Clocks The ML32x platform has two SMA clock inputs that allow connection to an external function generator These connect...

Page 14: ...connectors can also be used as eight single ended clock inputs Table 6 Differential Oscillator Pin Connections Label ML324 ML325 Clock Name Pin Clock Name Pin X2 CLK_BREF2_TOP_P CLK_BREF2_TOP_N K20 J2...

Page 15: ...indicate status or for any other purpose the user desires Table 8 User LEDs LED Row 1 LED Row 1 ML324 ML325 Pin Pin DS15 AK30 AT10 DS13 AL30 AV10 DS12 AN30 AW10 DS11 AM30 AR11 DS10 AT30 AP11 DS9 AL29...

Page 16: ...ns on the FPGA These DIP switches can be used to generate vectors or any other purpose that the user sees fit Table 10 User DIP Switches SW1 SW1 ML324 ML325 Pin Pin 1 AA10 AM2 2 AB10 AP2 3 AC10 AR2 4...

Page 17: ...w of header pins J49 to the left of J55 are connected to VCCO This gives the user the ability to jumper I O pins on J56 to GND and I O pins on J55 to either VCCO or GND Table 12 User Push Buttons Labe...

Page 18: ...42 N 24 R34 L39 P 47 AJ36 AM41 P 25 R39 M36 N 49 AJ35 AN42 N 26 R38 M35 P 51 AJ34 AN41 P 27 T38 N40 N 53 AJ39 AP42 N 28 T37 N39 P 55 AJ38 AP41 P 29 U35 R38 N 57 AK36 AT42 N 30 U34 R37 P 59 AK35 AT41 P...

Page 19: ...ed clock for each RocketIO transceiver as shown in Table 14 Note if these headers are not being used to monitor the clocks they may be used for any other purpose the user sees fit Table 14 Recovered C...

Page 20: ...NE pin on the FPGA This LED lights when DONE is high or if power is applied to the board without a part in the socket 16 INIT LED The INIT LED lights during initialization 17 Config Address DIP Switch...

Page 21: ...23 A24 A22 A21 A24 A25 A23 A22 7 A18 A19 A17 A16 A20 A21 A19 A18 8 A14 A15 A13 A12 A16 A17 A15 A14 9 A10 A11 A9 A8 A12 A13 A11 A10 10 A8 A9 A7 A6 11 A6 A7 A5 A4 A4 A5 A3 A2 14 AW6 AW7 AW5 AW4 BB4 BB5...

Page 22: ...17 The pins are set up in DTE mode as shown in Figure 3 Table 17 RS 232 Port Pins FPGA UART Port Name Direction Net ML324 ML325 TXD OUT T1IN AK25 AV34 RTS OUT T2IN AP26 AU34 RXD IN R1OUT AR26 AR34 CTS...

Page 23: ...AD2 P2 B1 DQ28 K1 E2 P8 VSSQ11 FILTERED GND FILTERED GND B2 VDDQ1 FILTERED VCCO FILTERED VCCO P7 VDDQ11 FILTERED VCCO FILTERED VCCO B3 VSSQ1 FILTERED GND FILTERED GND P3 VSSQ10 FILTERED GND FILTERED...

Page 24: ...ILTERED VCCO L9 VSSQ7 FILTERED GND FILTERED GND E1 VDDQ5 FILTERED VCCO FILTERED VCCO L8 DQ7 AB2 N1 E2 DQ31 H2 D1 L7 VDD3 VCCO VCCO E3 NC1 NC NC L3 VSS3 GND GND E7 NC2 NC NC L2 DQ8 AL2 AA3 E8 DQ16 V2 M...

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