Xilinx Virtex-II Pro ML324, User Manual

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Virtex-II Pro ML324 and ML325 Platform www.xilinx.com 19
UG063 (v1.2) May 30, 2006
Detailed Description
R
12. Recovered Clock Monitor Headers
There are 16 or 20 2-pin headers connected to user I/O pins near the top and bottom of the
FPGA. These headers are intended to be used to monitor the recovered clock for each
RocketIO transceiver as shown in
Table 14 . Note, if these headers are not being used to
monitor the clocks, they may be used for any other purpose the user sees fit.
Table 14: Recovered Clock Monitor Pins
Label
ML324 ML325
Pin Pin
J136 C11 C11
J135 D11 C15
J53 K13
J10 C14 F19
J30 C15 M21
J12 C22 H23
J39 C23 D24
J96 C29 L27
J50 F30
J134 C30 G31
J13 AU10 AT12
J54 AT13
J28 AU11 AY15
J140 AU14 AW19
J139 AU15 AV20
J137 AU22 AR23
J138 AU23 AY24
J20 AU29 AY28
J141 AU30
J11 AU30 AN31