Xilinx Virtex-6 FPGA, Getting Started

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Virtex-6 Getting Started Guide www.xilinx.com 43
UG533 (v1.4) November 15, 2010
Getting Started with the Base Reference Design
Getting Started with the Base Reference Design
The Base Reference Design targeting the ML605 evaluation board, will filter images that
are transferred via Ethernet between the evaluation board and a PC. The images are stored
in DDR3 SDRAM available on the evaluation board. The stored image is continuously read
from SDRAM and filtered by the LX240T FPGA. The resulting image is continuously
stored back in the DDR3 SDRAM. This filtered image is then retrieved by the Base
Reference Design Interface Software and displayed on a PC.
Figure 1-43 shows a block diagram of the base reference design that has been implemented
in the Virtex-6 LX240T FPGA. The reference design includes common functions for
Ethernet SGMII communication, external memory interface, UART, and control.
A DDR3 Memory Controller Block is used to store both the unfiltered and filtered images
in the DDR3 SDRAM. These images are sent from a PC via a series of Ethernet packets.
This memory controller is continuously reading, filtering, and storing images back into
this memory. The PC also periodically retrieves the filtered images via Ethernet for display.
The Ethernet Management section includes an on-chip hard coded MAC and a Packet
Processing Engine. This section provides a way to control various aspects of the demo,
transfer images between the demo board and a PC, and receive status from the demo. A
simple MDIO controller is implemented using a Xilinx PicoBlaze™ processor. The purpose
of this controller is to determine presence of an Ethernet link as well as its operating speed.
The Image Processing structure consists of a 5x5 pixel 2D FIR filter.
X-Ref Target - Figure 1-43
Figure 1-43: Base Reference Design Block Diagram
UG533_ 01_43 _121109
DDR3
DVI
Output
Inverse
Gamma
FIR
Filters
Host
Management
PicoBlaze
Gamma
Packet
Processing
Engine
PHY
MIG Memory Interface
Image Processing
Link
Status
Ethernet Management
Loopback
Test
System Status
System
Monitor
GTX
Transceiver
SGMII
PC
Ethernet
MDIO
GTXE1
TEMAC_SINGLE
Embedded
Tri-Mode
Ethernet
MAC