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2.1
Xilinx Spartan-6 FPGA LX9 FPGA
The Xilinx XC6SLX9-2CSG324C device designed onto the Spartan-6 FPGA LX9 MicroBoard is a member of
the logic-optimized Xilinx Spartan-6 LX FPGA family. This family is built on a mature 45 nm low-power
copper process technology that delivers the optimal balance of cost, power, and performance. The Spartan-6
LX family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of
built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices,
SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology,
advanced system-level power management modes, auto-detect configuration options, and enhanced IP security
with Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC
products with unprecedented ease-of-use. Spartan-6 FPGAs offer the best solution for high-volume logic
designs, consumer-oriented DSP designs, and cost-sensitive embedded applications.
On the Avnet Spartan-6 FPGA LX9 MicroBoard, the FPGA provides four I/O banks. Banks 0, 1, and 2 VCCO
as well as the VCCAUX power rail are tied to 3.3V. This allows Bank 0 to interface to 3.3V user I/O, Bank 1 to
interface to 3.3V Ethernet I/O, and Bank 2 to interface to 3.3V configuration I/O. Bank 3 interfaces to the
LPDDR memory and is connected to a 1.8V power rail for low-power consumption memory designs. The
VCCINT power rail is connected to 1.2V.
The four I/O banks are described in
Figure 4
and detailed I/O pin usage is provided throughout this document.
