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PCI32 Interface v3.0

6

www.xilinx.com

DS206 August 31, 2005

Product Specification v3.0.151

Target State Machine

This block controls the PCI interface target functions. The states implemented are a subset of those
defined in Appendix B of the 

PCI Local Bus Specification

. The target control logic uses one-hot encoding

for maximum performance.

Interface Configuration

The PCI Interface can be easily configured to fit unique system requirements using the Xilinx CORE
Generator GUI or by changing the HDL configuration file. The following customization options,
among many others, are supported by the interface and are described in the 

PCI User Guide.

Device and vendor ID

Base Address Registers (number, size, and type)

Burst Transfer

The PCI bus derives its performance from its ability to support burst transfers. The performance of any
PCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer
can efficiently be implemented using on-chip RAM resources.

Supported PCI Commands

Table 3

 illustrates the PCI bus commands supported by the PCI Interface.

Table  2:  

PCI Configuration Space Header 

31

16 15

0

Device ID

Vendor ID

00h

Status

Command

04h

Class Code

Rev ID

08h

BIST

Header 

Type

Latency 

Timer

Cache Line 

Size

0Ch

Base Address Register 0 (BAR0)

10h

Base Address Register 1 (BAR1)

14h

Base Address Register 2 (BAR2)

18h

Base Address Register 3 (BAR3)

1Ch

Base Address Register 4 (BAR4)

20h

Base Address Register 5 (BAR5)

24h

Cardbus CIS Pointer

28h

Subsystem ID

Subsystem Vendor ID

2Ch

Expansion ROM Base Address

30h

Reserved

CapPtr

34h

Reserved

38h

Max Lat

Min Gnt

Int Pin

Int Line

3Ch

Reserved

40h-FFh

Note

: Shaded areas are not implemented and return zero.

Summary of Contents for PCI32

Page 1: ...dBus compliant Supported initiator functions Configuration read configuration write Memory read memory write MRM MRL Interrupt acknowledge special cycles I O read I O write Supported target functions...

Page 2: ...l devices 0oC Tj 85oC Table 1 Core Implementation Supported Device Power Supply PCI32 66 Virtex XCV200 FG256 6C 3 3V only Virtex E XCV200E FG256 6C 3 3V only Virtex E XCV400E FG676 6C 3 3V only Virtex...

Page 3: ...y applications that need a PCI interface General Description The Xilinx PCI interface is a pre implemented and fully tested module for Xilinx FPGAs The pinout for each device and the relative placemen...

Page 4: ...lity and flexibility in PCI designs The Smart IP technol ogy is incorporated in every PCI interface Xilinx Smart IP technology leverages the Xilinx architectural advantages such as look up tables and...

Page 5: ...bility including the ability to implement a capabilities pointer in configuration space allows the user to implement functions such as power management and message signaled interrupts in the user appl...

Page 6: ...es its performance from its ability to support burst transfers The performance of any PCI application depends largely on the size of the burst transfer Buffers to support PCI burst transfer can effici...

Page 7: ...locked into one DMA engine hence an optimized design that fits a specific application can be designed Recommended Design Experience The PCI Interface is pre implemented allowing engineering focus on...

Page 8: ...s Timing Parameters in the 33 MHz Implementations Table 3 PCI Bus Commands CBE 3 0 Command PCI Initiator PCI Target 0000 Interrupt Acknowledge Yes Yes 0001 Special Cycle Yes Ignore 0010 I O Read Yes Y...

Page 9: ...oat 40 Notes 1 Controlled by timespec constraints included in product 2 Controlled by SelectIO configured for PCI66_3 3 Controlled by guide file included in product Table 5 Timing Parameters 33 MHz Im...

Page 10: ...tor system v7 1i or higher The Xilinx CORE Generator is bundled with the ISE Foundation v7 1i software at no additional charge To purchase the Xilinx PCI core please contact your local Xilinx sales re...

Page 11: ...refix to device names 1 30 04 1 9 Updated to build v3 0 122 updated copyright information to 2004 4 9 04 1 10 Updated to build v3 0 126 updated Xilinx tools to 6 2i SP1 in supported devices table adde...

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