Xilinx ML605 Hardware Tutorial Download Page 25

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ML605/SP605 Hardware Tutorial

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UG669 (v3.0) March 15, 2011

System Design Flow

Note:

Figure 13

shows the ML605 system.

X-Ref Target - Figure 13

Figure 13:

MicroBlaze Processor Subsystem with AXI_CDMA

FLA

(

2 MB)

FLA

RAM

Controller

Intern

l RAM

(

KB)

Micro

KB I & D C

che

MMU

Timer/

nter

Interr

Controller

AXI Interf

Monitor

Interr

GPIO

UART

16550

2 Line Driver/

Receiver

Ethernet

PHY

TriMode

Ethernet

MAC

LED

ition

l LED

tton

GPIO

wtiche

Memory

Proce

or Block

Inp

t/O

Micro

ze Proce

Sub

tem

Config

le U

er Logic

XC6VLX240T

IIC EEPROM

Memory

Controller

AXI

CDMA

Intern

BRAM

(64 KB)

PERF

AXI

EEPROM

DDR

(512 MB)

UG669_14_092910

Summary of Contents for ML605

Page 1: ...AXI Interface Based ML605 SP605 MicroBlaze Processor Subsystem Hardware Tutorial UG669 v3 0 March 15 2011...

Page 2: ...to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE D...

Page 3: ...reation 14 Opening the Project 14 Examining the System 15 Generating the Hardware Platform 21 Exporting the Base Hardware Platform to SDK 22 Downloading and Verifying the Design 23 Customizing the Emb...

Page 4: ...4 www xilinx com ML605 SP605 Hardware Tutorial UG669 v3 0 March 15 2011...

Page 5: ...A Additional information can be found in UG683 EDK Concepts Tools and Techniques Readers are encouraged to refer to UG683 during the execution of this tutorial Ref 1 Users should allow approximately t...

Page 6: ...Ref 4 Familiarity with the SP605 MicroBlaze Processor Subsystem documented in DS667 AXI Interface Based SP605 Embedded Kit MicroBlaze Processor Subsystem Data Sheet Ref 5 Familiarity with UG683 EDK C...

Page 7: ...e Tutorial_Sandbox directory contains the additional files necessary to build the benchmarking system To generate a new tutorial sandbox copy the Tutorial_Sandbox directory into the working area on th...

Page 8: ...n edkBmmFile_bd bmm system xml ise_top bit contains no bootloop system ucf SW HW hw_platform hw data BenchmarkDemo elf BenchmarkDemo SDK_Export Tutorial_Completed ML605_System SP605_System MicroBlaze_...

Page 9: ...eps 1 Connect a USB Type A to Mini B 5 pin cable between the ML605 or SP605 USB JTAG connector and the host computer 2 Verify that the USB cable is properly connected to the USB UART connection and th...

Page 10: ...module For SP605 cd SP605_Embedded_Kit SP605_System ready_for_download xmd XMD fpga f ise_top_download bit Note This command downloads the hardware bitstream into the FPGA but does not download the s...

Page 11: ...board XMD mwr 0x81420000 0xA The value written to this register is now reflected in the GPIO LEDs The next write changes the LED display XMD mwr 0x81420000 0x5 Note A read from this register always r...

Page 12: ...Test option 2 loops through the LEDS two times and returns to the menu when complete The Ethernet Loopback Test option 6 takes 30 seconds to complete after displaying the initial setup message The Eth...

Page 13: ...stem 9 Execute the chosen tests and then select 0 to exit Details about the test options can be found in the UG670 AXI Interface Based ML605 SP605 MicroBlaze Processor Subsystem Software Tutorial Ref...

Page 14: ...takes approximately two hours to complete Note All time estimates are subject to host computer system speed and can vary depending on how much time is spent executing the software applications Hardwar...

Page 15: ...s section of the tutorial Ref 1 Bus Interfaces 1 To examine the bus structure of the MicroBlaze Processor Subsystem select the System Assembly View tab and then select the Bus Interfaces tab along the...

Page 16: ...16 www xilinx com ML605 SP605 Hardware Tutorial UG669 v3 0 March 15 2011 System Design Flow X Ref Target Figure 6 Figure 6 Bus Interfaces View of the MicroBlaze Processor Subsystem UG669_06_021611...

Page 17: ...connections to that component are shown See Figure 7 Note The visibility of the port connections for the system are controlled by the Port Filters window shown in Figure 8 Many of the peripherals have...

Page 18: ...the workspace Click the to the left of microblaze_0 s Address Map to expand the address map as shown in Figure 9 This workspace is used to modify the addresses of peripherals in the system X Ref Targ...

Page 19: ...s are described in the System Configuration section of DS668 AXI Interface Based ML605 Embedded Kit MicroBlaze Processor Subsystem Data Sheet Ref 3 and DS667 AXI Interface Based SP605 Embedded Kit Mic...

Page 20: ...yed Select the tab to show the particular feature or parameter of interest Figure 11 shows the configuration GUI for the Dual_Timer_Counter core 6 Click Cancel to return to the System Assembly View be...

Page 21: ...the XPS project by selecting File Exit 2 In the Design Hierarchy window click ise_top STRUCTURE 3 In the Processes window right click Generate Programming File and select Run as shown in Figure 12 Not...

Page 22: ...ion files are stored in the following location For ML605 ML605_Embedded_Kit Tutorial_Sandbox HW Microblaze_Processor_SubSystem SDK SDK_Export For SP605 SP605_Embedded_Kit Tutorial_Sandbox HW Microblaz...

Page 23: ...None See Figure 3 7 Connect to the processor by entering the connect mb mdm command 8 To download and execute the test software application enter these commands at the XMD command prompt For ML605 XMD...

Page 24: ...pies data from one area of the main memory to another area of main memory The Perf_AXI core which is added to the system monitors this transaction through monitoring signals on the AXI interface maste...

Page 25: ...KB Microblaze 8 KB I D Caches MMU Dual Timer Counter Interrupt Controller AXI Interface AXI Interface Monitor Interrupt GPIO GPIO GPIO UART 16550 RS232 Line Driver Receiver Ethernet PHY TriMode Ether...

Page 26: ...t click the AXI Central DMA and select Add IP as shown in Figure 15 Note Warning messages in the console window about the axi_cdma_0 or other cores added into the system not being accessible from any...

Page 27: ...0x8460FFFF 6 Click OK Parameter and address configuration is complete for the AXI_CDMA core 7 In the Instantiate and Connect IP dialog which is automatically invoked select User will make necessary c...

Page 28: ...d C_MSTID_WIDTH are dependent on the connection of the AXI_CDMA master to the AXI interconnect The C_MSTID_WIDTH is the size of the signal for both ARVALID and ARREADY signals which depend on the numb...

Page 29: ...e added AXI_CDMA and Perf_AXI instances the instance names are changed as shown in Figure 16 2 Click the axi_cdma_0 name of the core and wait until the text becomes editable Enter AXI_Central_DMA and...

Page 30: ...e AXI_Central_DMA Core 1 Expand the AXI_Central_DMA core in the System Assembly View SAV of the XPS GUI by clicking the respective For ML605 Connect the M_AXI connection to the AXI_MM from the pull do...

Page 31: ...1 UG669 v3 0 March 15 2011 System Design Flow For SP605 Connect the M_AXI connection to the AXI_DMA_MM from the pull down menu as shown in Figure 18 X Ref Target Figure 18 Figure 18 Connecting AXI_Cen...

Page 32: ...ossbar which is different from the shared bus methodology all masters have access to all slaves For the ML605 system the AXI_CDMA master is connected to the AXI_MM interconnect The master only accesse...

Page 33: ...ock pins interrupts and signals for the PERF_AXI_Central_DMA In the Port Filters ensure that Defaults is selected 1 Click on the Ports tab at the top of the System Assembly View window 2 Expand the In...

Page 34: ...down menu 9 Expand the PERF_AXI_Central_DMA core by clicking the respective In the Name column for AXI_Clk select the net name sys_clk_s from the Net column from the pull down menu 10 Expand the BUS_...

Page 35: ...ise_top STRUCTURE and double click system_i system system xmp This invokes XPS for the XPS subsystem 7 In XPS invoke a Xilinx shell by selecting Project Launch Xilinx Shell 8 In the shell enter xmd an...

Page 36: ...XMD stop XMD rst 8 To download and execute the Web Server to test the design enter XMD dow Benchmark_Demo ready_for_download BenchmarkDemo elf XMD con 9 The UART output should be as shown in Figure 22...

Page 37: ...ML605 SP605 Hardware Tutorial www xilinx com 37 UG669 v3 0 March 15 2011 System Design Flow X Ref Target Figure 23 Figure 23 Initial Benchmarking Demonstration Web Page UG669_24_110410...

Page 38: ...ick Start Benchmark Graph to start requesting benchmarking data Data collected from the Web server appears in the text box below the buttons and the graph begins to show An example of the page with be...

Page 39: ...12 data points at a time After the maximum has been reached the oldest data point is dropped and the newest data point is added In the benchmarking demonstration Web page click Stop Benchmark Graph t...

Page 40: ...mbedded System Tools Reference Manual EDK 13 1 Chapter 9 Xilinx Microprocessor Debugger XMD 7 UG670 AXI Interface Based ML605 SP605 MicroBlaze Processor Subsystem Software Tutorial 8 UG029 ChipScope P...

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