ML52
x
User Guide
www.xilinx.com
UG225 (v2.1) August 4, 2010
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/02/07
1.0
Initial Xilinx release.
08/06/07
1.1
Removed
UG091, Xilinx Generic Interface (XGI) SuperClock Module User Guide
from
“Package Contents.”
Removed “Power Bus and Switches” diagram from
Figure 1
.
Added Power Supply Block Diagram,
Figure 3
. Updated Micron part number in
“18. DDR2 Memory,” page 21
. Corrected DDR to DDR2 throughout. Updated ML521
connections for A11 and A12 in
Table 15
. Corrected CK0N and CK0P pin numbers in
Table 15
.
04/17/08
2.0
Added GTX transceiver and FXT device information. Updated VCCINT for ML525 in
Table 2
. Modified the power brick connection in
Figure 3
for consistency and accuracy.
Added Voltage Adjust Potentiometer column in
Table 3
. Added Platform Cable USB to
“3. FPGA Configuration.”
Corrected ML521 pins in
Table 9
. Updated Infineon and
Micron part numbers in
“18. DDR2 Memory.”
Corrected numerous pins in
Table 15
.
Corrected CTS and RXD pins in
Table 18
. Corrected the RS232 and DB9 reference
designators in
Figure 4
. Corrected J113 and J135 column headings in
Table 19
.
Renumbered XGI pins in columns E and F and corrected XGI pin F27 description in
Table 20
. Renumbered XGI pins in columns A and B in
Table 22
. Several updates to
Table 23
.
08/04/10
2.1
Section
“Features,” page 10
: Corrected the number of pairs of transceiver SMA
connectors from “32 to 96” to “16 to 48.”
Figure 1, page 11
, corrected the number of
transceivers/SMAs in FF665 from 12/48 to 8/32, and the number of clocks/SMAs in
FF665 from 6/12 to 4/8. Section
“19. GTP/GTX Transceiver Clock Input SMAs,” page 25
,
removed material from introductory paragraph describing the lack of AC coupling.
Table 22, page 33
, corrected ML523 pin for signal XGI_SE_30 from AH32 to AH34.
R
electronic components distributor
