Xilinx ML52 Series, User Manual

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ML52 x User Guide www.xilinx.com 15
UG225 (v2.1) August 4, 2010
Detailed Description
R
listed in Table 3 . The power supply disable jumper must be installed before supplying an
external supply on its corresponding supply jack.
3. FPGA Configuration
The FPGA can only be configured in JTAG mode using one of the following options:
• Parallel Cable III cable
• Parallel Cable IV cable
• Platform Cable USB
• System ACE controller
For detailed information, see System ACE CompactFlash Solution [Ref 1] .
Using the configuration address DIP switches, one of eight bitstreams stored in the
CompactFlash memory card can be accessed through the on-board System ACE controller.
Note:
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
cable is used, thus causing no disruption in the JTAG chain.
4. Program Switch (Active-Low)
The active-Low program switch, when pressed, grounds the program pin on of the FPGA.
5. DONE LED
The DONE LED indicates the status of the DONE pin of the FPGA. The LED lights when
DONE is high, indicating the FPGA configured successfully.
6. INIT LED
The INIT LED lights during initialization.
Table 3: Power Supply Module Jumpers
GTP/GTX Power
Supply Name
(1)
Max Current
Rating
Typical Voltage
Voltage
Adj. Pot.
Jack
Disable
Jumper
Description
LXT FXT
MGTAVCC 3.0A 1.0V 1.0V R2 J104 J5
Powers all transceiver analog
circuits.
AVCCPLL 1.5A 1.2V 1.0V R4 J108 J7
Powers all transceiver PLL and
clock network.
AVTTTX 1.5A 1.2V 1.2V R1 J107 J4
Termination voltage for
transceiver transmitter.
AVTTRX 1.5A 1.2V 1.2V R3 J106 J6
Termination voltage for
transceiver receiver.
Notes:
1. The GTP/GTX transceiver power supply names might have the prefix MGT in other Xilinx documentation. Names with and
without the MGT prefix are synonymous to each other.
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