Xilinx MicroBlaze, Reference Manual

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MicroBlaze Processor Reference Guide www.xilinx.com 83
UG081 (v14.7)
Stream Link Interfaces
Stream Link Interfaces
MicroBlaze can be configured with up to 16 Fast Simplex Link (FSL) or AXI4-Stream interfaces,
each consisting of one input and one output port. The channels are dedicated uni-directional point-
to-point data streaming interfaces. The parameter
C_STREAM_INTERCONNECT
is used to select
FSL or AXI4.
For detailed information on the FSL interface, please refer to the Fast Simplex Link (FSL) Bus data-
sheet, DS449, in the Xilinx EDK IP Documentation. For detailed information on the AXI4-Stream
interface, please refer to the
AMBA
®
4 AXI4-Stream Protocol Specification, Version 1.0 document .
The interfaces on MicroBlaze are 32 bits wide. A separate bit indicates whether the sent/received
word is of control or data type. The get instruction in the MicroBlaze ISA is used to transfer
information from a port to a general purpose register. The put instruction is used to transfer data in
the opposite direction. Both instructions come in 4 flavors: blocking data, non-blocking data,
blocking control, and non-blocking control. For a detailed description of the get and put instructions,
please refer to
Chapter 5, MicroBlaze Instruction Set Architecture .
Hardware Acceleration
Each link provides a low latency dedicated interface to the processor pipeline. Thus they are ideal
for extending the processors execution unit with custom hardware accelerators. A simple example is
illustrated in
Figure 2-25 . The code uses RFSLx to indicate the used link, independent of whether
FSL or AXI4-Stream is used.
Figure 2-25: Stream Link Used with HW Accelerated Function
f
x
This method is similar to extending the ISA with custom instructions, but has the benefit of not
making the overall speed of the processor pipeline dependent on the custom function. Also, there are
no additional requirements on the software tool chain associated with this type of functional
extension.
MicroBlaze
Custom HW Accelerator
Link x
// Configure f
x
cput R c, RFSL x
// Store operands
put R a, RFSL x // op 1
put R b, RFSL x // op 2
// Load result
get R t, RFSL x
Example code:
Register
File
ConfigReg
Op1Reg Op2Reg
f
x
ResultReg
Link x
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