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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
Victim Cache
The victim cache is enabled by setting the parameter
C_ICACHE_VICTIMS
to 2, 4 or 8. This
defines the number of cache lines that can be stored in the victim cache. Whenever a cache line is
evicted from the cache, it is saved in the victim cache. By saving the most recent lines they can be
fetched much faster, should the processor request them, thereby improving performance. If the
victim cache is not used, all evicted cache lines must be read from memory again when they are
needed.
With the AXI4 interface,
C_ICACHE_DATA_WIDTH
determines the amount of data transferred
from/to the victim cache each clock cycle, either 32 bits or an entire cache line.
Note that to be able to use the victim cache, area optimization must not be enabled.
Instruction Cache Software Support
MSR Bit
The ICE bit in the MSR provides software control to enable and disable caches.
The contents of the cache are preserved by default when the cache is disabled. You can invalidate
cache lines using the WIC instruction or using the hardware debug logic of MicroBlaze.
WIC Instruction
The optional WIC instruction (
C_ALLOW_ICACHE_WR=1
) is used to invalidate cache lines in the
instruction cache from an application. For a detailed description, refer to
The WIC instruction can also be used together with parity protection to periodically invalidate
entries the cache, to avoid accumulating errors.
Data Cache
Overview
MicroBlaze can be used with an optional data cache for improved performance. The cached memory
range must not include addresses in the LMB address range. The data cache has the following
features:
•
Direct mapped (1-way associative)
•
Write-through or Write-back
•
User selectable cacheable memory address range
•
Configurable cache size and tag size
•
Caching over AXI4 interface (M_AXI_DC) or CacheLink (XCL) interface
•
Option to use 4 or 8 word cache-lines
•
Cache on and off controlled using a bit in the MSR
•
Optional WDC instruction to invalidate or flush data cache lines
•
Optional victim cache with write-back to improve performance by saving evicted cache lines
•
Optional parity protection for write-through cache that invalidates cache lines if a Block RAM
bit error is detected
•
Optional data width selection to either use 32 bits, an entire cache line, or 512 bits
