Xilinx MicroBlaze, Reference Manual

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MicroBlaze Processor Reference Guide www.xilinx.com 119
UG081 (v14.7)
Local Memory Bus (LMB) Interface Description
Read and Write Data Steering
The MicroBlaze data-side bus interface performs the read steering and write steering required to
support the following transfers:
•
byte, halfword, and word transfers to word devices
•
byte and halfword transfers to halfword devices
•
byte transfers to byte devices
MicroBlaze does not support transfers that are larger than the addressed device. These types of
transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze
bus interface. Data steering for read cycles are shown in
Table 3-6 and Table 3-7 , and data steering
for write cycles are shown in Table 3-8 and Table 3-9 .
Table 3-6: Big Endian Read Data Steering (Load to Register rD)
Address
[30:31]
Byte_Enable
[0:3]
Transfer
Size
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
11 0001 byte Byte3
10 0010 byte Byte2
01 0100 byte Byte1
00 1000 byte Byte0
10 0011 halfword Byte2 Byte3
00 1100 halfword Byte0 Byte1
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 3-7: Little Endian Read Data Steering (Load to Register rD)
Address
[30:31]
Byte_Enable
[0:3]
Transfer
Size
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
11 1000 byte Byte0
10 0100 byte Byte1
01 0010 byte Byte2
00 0001 byte Byte3
10 1100 halfword Byte0 Byte1
00 0011 halfword Byte2 Byte3
00 1111 word Byte0 Byte1 Byte2 Byte3
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