Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual Download Page 90

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MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com

UG257 (v1.1) December 5, 2007

Chapter 11:

Intel StrataFlash Parallel NOR Flash PROM

UCF Location Constraints

Address

Figure 11-2

provides the UCF constraints for the StrataFlash address pins, including the

I/O pin assignment and the I/O standard used.

Data

Figure 11-3

provides the UCF constraints for the StrataFlash data pins, including the I/O

pin assignment and the I/O standard used.

Figure 11-2:

UCF Location Constraints for StrataFlash Address Inputs

NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

UG257_11_02_060706

Figure 11-3:

UCF Location Constraints for StrataFlash Data I/Os

UG257_11_0

_060706

Summary of Contents for MIcroBlaze Development Spartan-3E 1600E Kit

Page 1: ...R MicroBlaze Development Kit Spartan 3E 1600E Edition User Guide UG257 v1 1 December 5 2007...

Page 2: ...TS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND...

Page 3: ...s 11 Configuration Methods Galore 11 Voltages for all Applications 11 Related Resources 11 Chapter 2 Switches Buttons and Knob Slide Switches 13 Locations and Labels 13 Operation 13 UCF Location Const...

Page 4: ...n Overview 41 Character LCD Interface Signals 42 Voltage Compatibility 42 Interaction with Intel StrataFlash 43 UCF Location Constraints 43 LCD Controller 44 Memory Map 44 Command Set 46 Operation 50...

Page 5: ...Analog Inputs 76 Programmable Pre Amplifier 77 Interface 77 Programmable Gain 77 SPI Control Interface 78 UCF Location Constraints 79 Analog to Digital Converter ADC 79 Interface 79 SPI Control Inter...

Page 6: ...trol 109 Reserve FPGA VREF Pins 109 Related Resources 109 Chapter 14 10 100 Ethernet Physical Layer Interface Ethernet PHY Connections 112 MicroBlaze Ethernet IP Cores 113 UCF Location Constraints 114...

Page 7: ...rnet PHY Magnetics and RJ 11 Connector 138 Voltage Regulators 140 FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections 142 FPGA I O Banks 0 and 1 Oscillators 144 FPGA I O...

Page 8: ...6 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 R...

Page 9: ...tors for the non FPGA components x Micron Technology Inc for the 32M x 16 DDR SDRAM x SMSC for the 10 100 Ethernet PHY x STMicroelectronics for the 16M x 1 SPI serial Flash PROM x Texas Instruments In...

Page 10: ...100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface x Chapter 15 Expansion Connectors describes the various connectors available on...

Page 11: ...processing applications The board highlights these features x Spartan 3E specific features i Parallel NOR Flash configuration i MultiBoot FPGA configuration from Parallel NOR Flash PROM i SPI serial F...

Page 12: ...parallel NOR Flash Intel StrataFlash i FPGA configuration storage i MicroBlaze code storage shadowing x 16 Mbits of SPI serial Flash STMicro i FPGA configuration storage i MicroBlaze code shadowing x...

Page 13: ...In typical applications the JTAG programming hardware resides off board or in a separate programming module such as the Xilinx Platform USB cable This USB port is for programming only and can not be...

Page 14: ...12 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 1 Introduction and Overview R...

Page 15: ...nects the FPGA pin to 3 3V a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there...

Page 16: ...he FPGA pin to generate a logic Low when the button is not pressed Figure 2 5 shows how to specify a pull down resistor within the UCF There is no active debouncing circuitry on the push button Figure...

Page 17: ...TER Operation The rotary push button switch integrates two different functions The switch shaft rotates and outputs values whenever the shaft turns The shaft can also be pressed acting as a push butto...

Page 18: ...the FPGA pin pulls the signal to a logic High The UCF constraints in Figure 2 9 describe how to define the pull up resistor The FPGA circuitry to decode the A and B inputs is simple but must consider...

Page 19: ...ches as shown in Figure 2 10 The LEDs are labeled LED7 through LED0 LED7 is the left most LED LED0 the right most LED Figure 2 8 Outputs from Rotary Shaft Encoder May Include Mechanical Chatter A B De...

Page 20: ...e and the output drive current Related Resources x Rotary Encoder Interface for Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter http www xilinx com sp3e1600E Figure 2 10 Eight D...

Page 21: ...lock oscillator x The user clock socket is populated with a 66 MHz oscillator x Clocks can be supplied off board via an SMA style connector Alternatively the FPGA can generate clock signals or other h...

Page 22: ...P footprint Use this socket if the FPGA application requires a frequency other than 50 MHz This socket is populated with a 66 MHz oscillator This clock input is used for some of the reference designs...

Page 23: ...xample constraint appears in Figure 3 3 for the on board 50 MHz clock oscillator The CLK_50MHZ frequency is 50 MHz which equates to a 20 ns period The output duty cycle from the oscillator ranges betw...

Page 24: ...22 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 3 Clock Sources R...

Page 25: ...ored in the Platform Flash PROM using Master Serial mode x Program the on board 16 Mbit ST Microelectronics SPI serial Flash PROM then configure the FPGA from the image stored in the SPI serial Flash...

Page 26: ...latform Flash PROM mode pins 128 Mbit Intel StrataFlash Parallel NOR Flash Memory Byte Peripheral Interface BPI mode UG257_04_01_061306 4 Mbit Xilinx Platform Flash PROM Configuration storage for Mast...

Page 27: ...ation modes and loading the FPGA from the StrataFlash parallel Flash PROM The CPLD is user programmable Configuration Mode Jumpers As shown in Table 4 1 the J30 jumper block settings control the FPGA...

Page 28: ...4 2 page 24 lights whenever the FPGA is successfully configured If this LED is not lit then the FPGA is not configured BPI Down see Chapter 11 Intel StrataFlash Parallel NOR Flash PROM 011 StrataFlash...

Page 29: ...tandard USB Type A Type B cable similar to the one shown in Figure 4 3 The actual cable color might vary from the picture The wider and narrower Type A connector fits the USB connector at the back of...

Page 30: ...ng connect the USB cable to the starter kit board and apply power to the board Then double click Configure Device iMPACT from within Project Navigator as shown in Figure 4 5 If the board is connected...

Page 31: ...clock source To start programming the FPGA right click the FPGA and select Program The iMPACT software reports status during programming process Direct programming to the FPGA takes a few seconds to...

Page 32: ...ration Bitstream File Before generating the PROM file create the FPGA bitstream file The FPGA provides an output clock CCLK when loading itself from an external PROM The FPGA s internal CCLK oscillato...

Page 33: ...ptions as shown in Figure 4 11 Using the Configuration Rate drop list choose 25 to increase the internal CCLK oscillator to approximately 25 MHz the fastest frequency when using an XCF04S Platform Fla...

Page 34: ...ing File as shown in Figure 4 12 Generating the PROM File After generating the program file double click Generate PROM ACE or JTAG File to launch the iMPACT software as shown in Figure 4 13 After iMPA...

Page 35: ...linx PROM as the target PROM type as shown in Figure 4 15 Select from any of the PROM File Formats the Intel Hex format MCS is popular Enter the Location of the directory and the PROM File Name Click...

Page 36: ...arter Kit board has an XCF04S Platform Flash PROM Select xcf04s from the drop list as shown in Figure 4 16 Click Add then click Next The PROM Formatter then echoes the settings as shown in Figure 4 17...

Page 37: ...art selecting files Select an FPGA bitstream file bit Choose No after selecting the last FPGA file Finally click OK to continue When PROM formatting is complete the iMPACT software presents the presen...

Page 38: ...ns R To generate the actual PROM file click Operations Generate File as shown in Figure 4 20 The iMPACT software indicates that the PROM file was successfully created as shown in Figure 4 21 Figure 4...

Page 39: ...ted PROM file into the Platform Flash PROM via the on board USB JTAG circuitry follow the steps outlined in this subsection Place the iMPACT software in the JTAG Boundary Scan mode either by choosing...

Page 40: ...iguration File Select a previously generated PROM format file and click OK To start programming the PROM right click the PROM icon and then click Program The programming software again prompts for the...

Page 41: ...are recommended even though they increase overall programming time The Load FPGA option immediately forces the FPGA to reconfigure after programming the Platform Flash PROM The FPGA s configuration mo...

Page 42: ...40 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 4 FPGA Configuration Options R...

Page 43: ...n be attached to this connector The Spartan 3E MicroBlaze Development Kit board prominently features a 2 line by 16 character liquid crystal display LCD The FPGA controls the LCD via the 4 bit data in...

Page 44: ...cepts 5V TTL signal levels and the 3 3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements The 390 series resistors on the data lines prevent overstressing on the FPGA and...

Page 45: ...taFlash Control Interaction SF_CE0 SF_BYTE LCD_RW Operation 1 X X StrataFlash disabled Full read write access to LCD X X 0 LCD write access only Full access to StrataFlash X 0 X StrataFlash in byte wi...

Page 46: ...er line Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non display data Alternatively these locations can also store characters that can only displayed using controller s...

Page 47: ...bitmaps stored in CG RAM These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location CG RAM The Character Generator RAM CG RAM provides space to creat...

Page 48: ...ata bits are used the upper three data bits are don t care positions The eighth row of bitmap data is usually left as all zeros to accommodate the cursor Command Set Table 5 3 summarizes the available...

Page 49: ...ition shown in Figure 5 3 The address counter is reset to 0 location 0x00 in DD RAM The display is returned to its original status if it was shifted The cursor or blink move to the top left character...

Page 50: ...or position or display to the right or left without writing or reading display data This function positions the cursor in order to modify an individual character or to scroll the display window left o...

Page 51: ...operation is in progress The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute This command also returns the present value of...

Page 52: ...Address command After the read operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command However a display shift is not executed during read opera...

Page 53: ...ideally suited to the highly efficient 8 bit PicoBlaze embedded controller After initialization the PicoBlaze controller is available for more complex control or computation beyond simply driving the...

Page 54: ...and each character is automatically stored and displayed in the next available location Continuing to write characters however eventually falls off the end of the first display line The additional ch...

Page 55: ...r line has a series resistor with one bit each for VGA_RED VGA_GREEN and VGA_BLUE The series resistor in combination with the 75 termination built into the VGA cable ensures that the color signals rem...

Page 56: ...cross a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCDs have evolved...

Page 57: ...ble colors shown in Table 6 1 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely th...

Page 58: ...e pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical...

Page 59: ...and the output drive current Related Resources x VESA http www vesa org x VGA timing information http www epanorama net documents pc vga_timing html Figure 6 4 UCF Constraints for VGA Display Port NE...

Page 60: ...58 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 6 VGA Display Port R...

Page 61: ...trol other RS 232 peripherals such as modems or printers or perform simple loopback testing with the DCE connector Figure 7 1 shows the connection between the FPGA and the two DB9 connectors The FPGA...

Page 62: ...ale DB9 1 2 3 4 5 6 7 8 9 GND 1 2 3 4 5 6 7 8 9 GND RS232_DCE_RXD RS232_DCE_TXD RS232_DTE_TXD RS232_DTE_RXD DCE Female DB9 RS 232 Voltage Translator IC2 J9 J10 M13 U8 M14 R7 Pin 1 Pin 6 Pin 9 Pin 5 DB...

Page 63: ...s respectively including the I O pin assignment and the I O standard used Figure 7 2 UCF Location Constraints for DTE RS 232 Serial Port Figure 7 3 UCF Location Constraints for DCE RS 232 Serial Port...

Page 64: ...62 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 7 RS 232 Serial Ports R...

Page 65: ...tor labeled J14 on the board Figure 8 1 shows the PS 2 connector and Table 8 1 shows the signals on the connector Only pins 1 and 5 of the connector attach to the FPGA Figure 8 1 PS 2 Connector Locati...

Page 66: ...clock signal is High and the host reads the data line when the clock signal is Low Keyboard The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus...

Page 67: ...R 2D T 2C A 1C S 1B D 23 F 2B G 34 Z 1Z X 22 C 21 V 2A B 32 6 36 7 3D 8 3E 9 46 0 45 _ 4E 55 Back Space 66 Y 35 U 3C I 43 O 44 P 4D 54 5B 5D H 33 J 3B K 42 L 4B 4C 52 Enter 5A N 31 M 3A 41 49 4A Shif...

Page 68: ...t data fields contain movement data as shown in Figure 8 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 kHz A PS 2 style mouse employs a relative coordinate system s...

Page 69: ...by 5V Although the Spartan 3E FPGA is not a 5V tolerant device it can communicate with a 5V device using series current limiting resistors as shown in Figure 8 1 UCF Location Constraints Figure 8 6 pr...

Page 70: ...68 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 8 PS 2 Mouse Keyboard Port R...

Page 71: ...r as shown in Figure 9 1 SPI Communication As shown in Figure 9 2 the FPGA uses a Serial Peripheral Interface SPI to communicate digital values to each of the four DAC channels The SPI bus is a full d...

Page 72: ...are shared by other devices on the board It is vital that other devices are disabled when the FPGA communicates with the DAC to avoid bus contention Table 9 2 provides the signals and logic values re...

Page 73: ...edge The FPGA must read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low Otherwise bit 31 is missed After transmitting all 32 data bits the FPGA completes the SPI bus t...

Page 74: ...g equivalent of a 12 bit unsigned digital value D 11 0 written by the FPGA to the DAC via the SPI interface The voltage on a specific output is generally described in Equation 9 1 The reference voltag...

Page 75: ...ocument do navId H0 C1 C1155 C1005 C1156 P2048 D2170 x PicoBlaze Based D A Converter Control for the Spartan 3E Starter Kit Reference Design x http www xilinx com sp3e1600e x Xilinx PicoBlaze Soft Pro...

Page 76: ...74 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 9 Digital to Analog Converter DAC R...

Page 77: ...alog capture circuit consists of a Linear Technology LTC6912 1 programmable pre amplifier that scales the incoming analog signal on header J7 see Figure 10 2 The output of pre amplifier connects to a...

Page 78: ...INB The maximum range of the ADC is r1 25V centered around the reference voltage 1 65V Hence 1 25V appears in the denominator to scale the analog input accordingly Finally the ADC presents a 14 bit tw...

Page 79: ...l has an associated programmable gain amplifier see Figure 10 2 Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative to 1 65V The 1 65V reference is generated using...

Page 80: ...on SPI_MOSI on the rising edge of the SPI_SCK clock signal The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK The amplifier interface is relatively slow supporting only abo...

Page 81: ...the ADC When the AD_CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD_CONV is asserted a latency of one...

Page 82: ...n assignment and I O standard used Figure 10 6 Analog to Digital Conversion Interface Figure 10 7 Detailed SPI Timing to ADC Spartan 3E FPGA Master 60 61 62 63 64 65 66 67 68 69 610 611 612 613 60 61...

Page 83: ...pacitor Related Resources x Amplifier and A D Converter Control for the Spartan 3E Starter Kit Reference Design x http www xilinx com sp3e1600e x Xilinx PicoBlaze Soft Processor x http www xilinx com...

Page 84: ...82 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 10 Analog Capture Circuit R...

Page 85: ...he StrataFlash device x Stores two different FPGA configurations in the StrataFlash device and dynamically switch between the two using the Spartan 3E FPGA s MultiBoot feature x Stores and executes Mi...

Page 86: ...only requires just slightly under 6 Mbits per configuration image the FPGA to StrataFlash interface on the board support up to a 256 Mbit StrataFlash The MicroBlaze Development Kit board ships with a...

Page 87: ...ves these pins during FPGA configuration as described in Chapter 16 XC2C64A CoolRunner II CPLD Also connects to FPGA user I O pins SF_A24 is the same as FX2 connector signal FX2_IO 32 SF_A23 N11 SF_A2...

Page 88: ...D4 U9 SF_D3 V9 SF_D2 R10 SF_D1 P10 SPI_MISO N10 Bit 0 of data byte and 16 bit halfword Connects to FPGA pin D0 DIN to support the BPI configuration Shared with other SPI peripherals and Platform Flash...

Page 89: ...n The most significant address line SF_A 24 is not physically used on the 16 Mbyte StrataFlash PROM It is provided for upward migration to a larger StrataFlash PROM in the same package footprint Likew...

Page 90: ...LEW SLOW NET SF_A 9 LOC K12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 8 LOC K15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 7 LOC K14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 6 LOC J17 I...

Page 91: ...4 UCF Location Constraints for StrataFlash Control Pins NET SF_BYTE LOC C17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_CE0 LOC D16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_OE LOC C18 IOSTANDARD...

Page 92: ...90 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM R...

Page 93: ...x Simple non volatile data storage x Storage for identifier codes serial numbers IP addresses etc x Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM Figure 12 1 Spartan 3E FPG...

Page 94: ...UCF Location Constraints for SPI Flash Connections some connections shared with SPI Flash DAC ADC and AMP NET SPI_MISO LOC N10 IOSTANDARD LVCMOS33 NET SPI_MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRI...

Page 95: ...ration clock rate when connected to an M25P16 SPI serial Flash Set the Properties for Generate Programming File so that the Configuration Rate is 12 as shown in Figure 12 5 See Generating the FPGA Con...

Page 96: ...ROM File Formatter as shown in Figure 12 7 Choose 3rd Party SPI PROM as the target PROM type as shown in Figure 12 8 Select from any of the PROM File Formats the Intel Hex format MCS is popular The PR...

Page 97: ...com Configuring from SPI Flash R The Spartan 3E Starter Kit board has a 16 Mbit SPI serial Flash PROM Select 16M from the drop list as shown in Figure 12 9 Click Next Figure 12 8 Choose the PROM Targ...

Page 98: ...les Select an FPGA bitstream file bit Choose No after selecting the last FPGA file Finally click OK to continue When PROM formatting is complete the iMPACT software presents the present settings by sh...

Page 99: ...n Figure 12 13 As shown in Figure 12 14 the iMPACT software indicates that the PROM file was successfully created The PROM Formatter creates an output file based on the settings shown in Figure 12 8 I...

Page 100: ...cted to the FPGA See the link to the Universal Scan SPI Flash programming tutorial in Related Resources page 104 x Additional programming support will be provided in the ISE 8 2i software Downloading...

Page 101: ...oward the J11 jumpers If using flying leads they must be connected as shown in Figure 12 15 b and Table 12 2 Note the color coding for the leads The gray INIT lead is left unconnected Insert Jumper on...

Page 102: ...ss the Enter key to continue The entire programming process takes slightly longer than a minute as shown in Figure 12 17 Figure 12 16 Installing the JP8 Jumper Holds the FPGA in Configuration State PR...

Page 103: ...iguration pins are available to the application On the Spartan 3E Starter Kit board the SPI bus is shared by other SPI capable peripheral devices as shown in Figure 12 18 To access the SPI Flash memor...

Page 104: ...es the option to move the on board SPI Flash to a different select line SPI_ALT_CS_JP11 This way a different SPI Flash device can be tested by changing the JP11 jumper settings and connecting the alte...

Page 105: ...ckage footprint supports the XC3S500E the XC3S1200E and the XC3S1600E FPGA devices without modification The SPI Flash multi package layout allows comparable flexibility in the associated configuration...

Page 106: ...s x http www xilinx com xlnx xebiz productview jsp sGlobalNavPick category 19314 x Digilent JTAG3 Programming Cable x http www digilentinc com Products Catalog cfm Nav1 Products Nav2 Cables C at Cable...

Page 107: ...tor from the board s 5V supply input The 1 25V reference voltage common to the FPGA and DDR SDRAM is generated using a resistor voltage divider from the 2 5V rail All DDR SDRAM interface signals are t...

Page 108: ...icroBlaze OPB DDR controller The MicroBlaze OPB DDR SDRAM controller IP core documentation is also available from within the EDK 8 1i development software see Related Resources page 109 DDR SDRAM Conn...

Page 109: ...BA1 K6 Bank address inputs SD_BA0 K5 SD_RAS C1 Command inputs SD_CAS C2 SD_WE D1 SD_CK_N J4 Differential clock input SD_CK_P J5 SD_CKE K3 Active High clock enable input SD_CS K4 Active Low chip select...

Page 110: ...A 6 LOC H3 IOSTANDARD SSTL2_I NET SD_A 5 LOC H4 IOSTANDARD SSTL2_I NET SD_A 4 LOC E4 IOSTANDARD SSTL2_I NET SD_A 3 LOC P1 IOSTANDARD SSTL2_I NET SD_A 2 LOC R2 IOSTANDARD SSTL2_I NET SD_A 1 LOC R3 IOST...

Page 111: ...roBlaze OPB Double Data Rate DDR SDRAM Controller v2 00b http www xilinx com bvdocs ipcenter data_sheet opb_ddr pdf Figure 13 4 UCF Location Constraints for DDR SDRAM Control Pins NET SD_BA 0 LOC K5 I...

Page 112: ...110 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 13 DDR SDRAM R...

Page 113: ...physical layer PHY interface and an RJ 45 connector as shown in Figure 14 1 With an Ethernet Media Access Controller MAC implemented in the FPGA the board can optionally connect to a standard Etherne...

Page 114: ...net PHY Signal Name FPGA Pin Number Function E_TXD 4 R6 Transmit Data to the PHY E_TXD 4 is also the MII Transmit Error E_TXD 3 T5 E_TXD 2 R5 E_TXD 1 T15 E_TXD 0 R11 E_TX_EN P15 Transmit Enable E_TX_C...

Page 115: ...upts back to back data transfers and statistics counters The Ethernet MAC core requires design constraints to meet the required performance Refer to the OPB Ethernet MAC data sheet v1 02 for details T...

Page 116: ...ideal for applications the do not require support for interrupts back to back data transfers and statistics counters x http www xilinx com bvdocs ipcenter data_sheet opb_ethernetlite pdf x EDK 8 1i D...

Page 117: ...along the right edge of the board see Figure 15 1 This connector is a Hirose FX2 100P 1 27DS header with 1 27 mm pitch Throughout the documentation this connector is called the FX2 connector As shown...

Page 118: ...changed to 2 5V using jumper JP9 Some FPGA I O standards especially the differential standards such as RSDS and LVDS require a 2 5V output supply voltage To support high speed signals across the conne...

Page 119: ...GND FX2_IO3 D5 8 8 GND GND FX2_IO4 C5 9 9 GND GND FX2_IO5 A6 10 10 GND GND FX2_IO6 B6 11 11 GND GND FX2_IO7 E7 12 12 GND GND FX2_IO8 F7 13 13 GND GND FX2_IO9 D7 14 14 GND GND FX2_IO10 C7 15 15 GND GN...

Page 120: ...erential I O pairs and two input only pairs using either the LVDS or RSDS I O standards as listed in Table 15 2 All I O pairs support differential input termination DIFF_TERM as described in the FX2_I...

Page 121: ...N_0 I O Yes FX2_IO4 C5 IO_L23P_0 I O Yes 3 FX2_IO5 A6 IO_L20N_0 I O Yes FX2_IO6 B6 IO_L20P_0 I O Yes 4 FX2_IO7 E7 IO_L19N_0 I O Yes FX2_IO8 F7 IO_L19P_0 I O Yes 5 FX2_IO9 D7 IO_L18N_0 I O Yes FX2_IO10...

Page 122: ...available on differential I O signals Each differential I O pin includes a circuit that behaves like an internal termination resistor of approximately 120 On chip differential termination is only avai...

Page 123: ...tion to power I O Bank 0 with either 3 3V or 2 5V Figure 15 1 page 115 highlights the location of jumper JP9 If using differential outputs on the FX2 connector set jumper JP9 to 2 5V If the jumper is...

Page 124: ...SLEW FAST DRIVE 8 NET FX2_IO 15 LOC D11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 16 LOC C11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 17 LOC F11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NE...

Page 125: ...90 socket Four FPGA pins connect to the J1 header J1 4 1 The board supplies 3 3V to the accessory board mounted in the J1 socket on the bottom pin Header J2 The J2 header shown in Figure 15 9 is the...

Page 126: ...eader J4 R14 J4 0 J4 1 J4 2 J4 3 T14 R13 P13 Spartan 3E FPGA GND 3 3V UG257_15_10_082907 Figure 15 11 UCF Location Constraints for Accessory Headers 6 pin header J1 These four connections are shared w...

Page 127: ...on the ChipScope Pro tool probes and connectors Table 15 3 provides the connector pinout Only 18 FPGA pins attach to the connector the remaining connector pads are unconnected All 18 FPGA pins are sh...

Page 128: ...c com Products Catalog cfm Nav1 Products Nav2 Peripheral Cat Peripheral x Xilinx ChipScope Pro Tool http www xilinx com ise optional_prod cspro htm x Agilent B4655A FPGA Dynamic Probe for Logic Analyz...

Page 129: ...n the BPI Down configuration mode FPGA_M 2 0 011 DONE 0 set the upper five StrataFlash PROM address lines A 24 20 to 11111 binary Set the upper five address lines to ZZZZZ for all non BPI configuratio...

Page 130: ...C_D 1 XC_D 0 P36 P34 P33 P8 P6 F17 F18 G16 T10 V11 FPGA_M2 FPGA_M1 P5 M10 FPGA_M0 XC_CPLD_EN XC_TRIG P42 P41 D10 R17 XC_DONE P40 DONE XC_PROG_B P39 PROG_B XC_GCK0 P43 GCLK10 H16 C9 P1 SPI_SCK P44 U16...

Page 131: ...F_A 24 LOC A11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 23 LOC N11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 22 LOC V12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 21 LOC V13 IOSTANDARD...

Page 132: ...C64A CoolRunner II CPLD R Related Resources x CoolRunner II CPLD Family Data Sheet http direct xilinx com bvdocs publications ds090 pdf x XC2C64A CoolRunner II CPLD Data Sheet http direct xilinx com b...

Page 133: ...PP780 listed under Related Resources provides one possible implementation method UCF Location Constraints Figure 17 2 provides the UCF constraints for the FPGA connections to the DS2432 SHA 1 EEPROM i...

Page 134: ...132 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Chapter 17 DS2432 1 Wire SHA 1 EEPROM R...

Page 135: ...ort x Ethernet PHY Magnetics and RJ 11 Connector x Voltage Regulators x FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections x FPGA I O Banks 0 and 1 Oscillators x FPGA I...

Page 136: ...d J3B are the connections to the FX2 expansion connector located along the right edge of the board Header J5 provides the four analog outputs from the Digital to Analog Converter DAC Header J6 is the...

Page 137: ...Development Kit Spartan 3E 1600 Edition User Guide 135 UG257 v1 1 December 5 2007 www xilinx com FX2 Expansion Header 6 pin Headers and Connectorless Probe Header R Figure 18 1 Schematic Sheet 1 UG257...

Page 138: ...e Chapter 8 PS 2 Mouse Keyboard Port for additional information Connector J15 is a VGA connector suitable for driving most VGA compatible monitors and flat screen displays See Chapter 6 VGA Display Po...

Page 139: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 137 UG257 v1 1 December 5 2007 www xilinx com RS 232 Ports VGA Port and PS 2 Port R Figure 18 2 Schematic Sheet 2 UG257_A02_060606...

Page 140: ...hernet PHY Magnetics and RJ 11 Connector IC6 is an SMSC 10 100 Ethernet PHY with its associated 25 MHz oscillator The PHY requires an Ethernet MAC implemented within the FPGA J19 is the RJ 11 Ethernet...

Page 141: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 139 UG257 v1 1 December 5 2007 www xilinx com Ethernet PHY Magnetics and RJ 11 Connector R Figure 18 3 Schematic Sheet 4 UG257_A03_060606...

Page 142: ...3 3V to other components on the board and to the FPGA s VCCO supply inputs on I O Banks 0 1 and 2 Jumpers JP6 and JP7 provide a means to measure current across the FPGA s VCCAUX and VCCINT supplies re...

Page 143: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 141 UG257 v1 1 December 5 2007 www xilinx com Voltage Regulators R Figure 18 4 Schematic Sheet 5 UG257_A04_060606...

Page 144: ...ted on the XC3S500E version of the board Resistor R100 jumpers over the JTAG chain bypassing the second XCF04S PROM Jumper header J30 selects the FPGA s configuration mode See Table 4 1 page 25 for ad...

Page 145: ...nt Kit Spartan 3E 1600 Edition User Guide 143 UG257 v1 1 December 5 2007 www xilinx com FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections R Figure 18 5 Schematic Sheet...

Page 146: ...presents the connections to I O Bank 0 on the FPGA The VCCO input to Bank 0 is 3 3V by default but can be set to 2 5V using jumper JP9 IC10B1 represents the connections to I O Bank 1 on the FPGA IC17...

Page 147: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 145 UG257 v1 1 December 5 2007 www xilinx com FPGA I O Banks 0 and 1 Oscillators R Figure 18 6 Schematic Sheet 7 UG257_A06_060606...

Page 148: ...3 IC10B2 represents the connections to I O Bank 2 on the FPGA Some of the I O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC IC10B3 represents the connections to I O Ba...

Page 149: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 147 UG257 v1 1 December 5 2007 www xilinx com FPGA I O Banks 2 and 3 R Figure 18 7 Schematic Sheet 8 UG257_A07_060606...

Page 150: ...matics R Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the power decoupling network Jumper JP9 defines the voltage applied to VCCO on I O Bank 0 Th...

Page 151: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 149 UG257 v1 1 December 5 2007 www xilinx com Power Supply Decoupling R Figure 18 8 Schematic Sheet 9 UG257_A08_060606...

Page 152: ...inx XC2C64A CoolRunner II CPLD The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations When the CPLD is loaded with the...

Page 153: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 151 UG257 v1 1 December 5 2007 www xilinx com XC2C64A CoolRunner II CPLD R Figure 18 9 Schematic Sheet 10 UG257_A09_060606...

Page 154: ...DAC IC19 is a Linear Technology LTC1407A 1 two channel ADC IC20 is a Linear Technology LTC6912 programmable pre amplifier AMP to condition the analog inputs to the ADC See Chapter 10 Analog Capture Ci...

Page 155: ...MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide 153 UG257 v1 1 December 5 2007 www xilinx com Linear Technology ADC and DAC R Figure 18 10 Schematic Sheet 11 UG257_A10_060606...

Page 156: ...atics R Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM IC22 is a 128 Mbit 16 Mbyte Intel StrataFlash parallel NOR Flash PROM See Chapter 11 Intel StrataFlash Parallel NOR Flash PROM...

Page 157: ...evelopment Kit Spartan 3E 1600 Edition User Guide 155 UG257 v1 1 December 5 2007 www xilinx com Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM R Figure 18 11 Schematic Sheet 12 UG257...

Page 158: ...coder and Character LCD SW0 SW1 SW2 and SW3 are slide switches Push button switches W E S and N are located around the ROT1 push button switch rotary encoder LD0 through LD7 are discrete LEDs See Chap...

Page 159: ...oBlaze Development Kit Spartan 3E 1600 Edition User Guide 157 UG257 v1 1 December 5 2007 www xilinx com Buttons Switches Rotary Encoder and Character LCD R Figure 18 12 Schematic Sheet 13 UG257_A12_06...

Page 160: ...Differential Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM See Chapter 13 DDR SDRAM for additional information Resistors R202 through R210 are no...

Page 161: ...lopment Kit Spartan 3E 1600 Edition User Guide 159 UG257 v1 1 December 5 2007 www xilinx com DDR SDRAM Series Termination and FX2 Connector Differential Termination R Figure 18 13 Schematic Sheet 14 U...

Page 162: ...160 MicroBlaze Development Kit Spartan 3E 1600 Edition User Guide www xilinx com UG257 v1 1 December 5 2007 Appendix A Schematics R...

Page 163: ...ANDARD LVCMOS33 GCLK8 Populated with 66MHz Osc Define clock period for 66 MHz oscillator 50 50 duty cycle NET CLK_AUX_66MHZ PERIOD 14 9ns HIGH 50 NET CLK_SMA LOC A10 IOSTANDARD LVCMOS33 RS 232 Serial...

Page 164: ...NET SF_D 12 LOC M16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D 13 LOC P6 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D 14 LOC R8 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D 15 LOC T8 IOSTANDAR...

Page 165: ...C K5 IOSTANDARD SSTL2_I NET SD_BA 1 LOC K6 IOSTANDARD SSTL2_I NET SD_CAS LOC C2 IOSTANDARD SSTL2_I NET SD_CK_N LOC J4 IOSTANDARD SSTL2_I NET SD_CK_P LOC J5 IOSTANDARD SSTL2_I NET SD_CKE LOC K3 IOSTAND...

Page 166: ...4 SLEW SLOW NET SF_A 24 LOC A11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_BYTE LOC C17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_CE0 LOC D16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D 1 LOC...

Page 167: ...T DRIVE 8 NET FX2_IO 22 LOC B13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 23 LOC A14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 24 LOC B14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO...

Page 168: ...LDOWN IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET INPUT_IO 7 LOC F10 PULLDOWN IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET INPUT_IO 8 LOC G10 PULLDOWN IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET INPUT_IO 9 L...

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