Xilinx MIcroBlaze Development Spartan-3E 1600E Kit, User Manual

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70 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
www.xilinx.com UG257 (v1.1) December 5, 2007
Chapter 9: Digital to Analog Converter (DAC)
R
Interface Signals
Table 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2 provides the signals and logic values required to disable the other devices.
Figure 9-2:
Digital-to-Analog Connection Schematics
He a der J5
DAC A
12
DAC B
12
DAC C
12
12
S PI_MO S I
DAC_C S
S PI_ S CK
DAC_CLR
C S /LD
S DI
S CK
CLR
S DO
S PI_MI S O
(N10) (T4)
(U16)
(P8)
(N8)
3 . 3 V
2.5V
A
B
C
D
GND
VCC
REF A
REF B
REF C
REF D
VOUTA
VOUTB
VOUTC
VOUTD
S p a rt a n- 3 E FPGA
DAC D
LTC 2624 DAC
S PI Control Interf a ce
( 3 . 3 V)
UG257_09_02_060606
Table 9-1:
DAC Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGA Æ DAC Serial data: Master Output, Slave Input
DAC_CS N8 FPGA
Æ
DAC Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
SPI_SCK U16 FPGA
Æ
DAC Clock
DAC_CLR P8 FPGA
Æ
DAC Asynchronous, active-Low reset input
SPI_MISO N10 FPGA Å DAC Serial data: Master Input, Slave Output