PCI v3.0.151 Getting Started Guide
www.xilinx.com
43
UG157 August 31, 2005
R
Chapter 5
Synthesizing a Design
This chapter describes how to synthesize the
ping64
example design with global clocks
using the supported synthesis tools. For the PCI 32 interface, substitute
ping32
for
ping64
. If
you are using a design with reference clocks, substitute
pcim_top
with
pcim_top_r
and
ping_tb
with
ping_tb_r
.
Supported synthesis tools include
•
Synplicity Synplify v7.3
•
Exemplar LeonardoSpectrum v2003a
•
Xilinx XST
Synplicity Synplify
Before attempting to synthesize a design, ensure that the Synplicity Synplify environment
is properly configured.
Verilog
1.
Start Synplify and choose File > New, or click the new file icon on the toolbar. The New
dialog box appears.
2.
Under File Type, select Project File and enter the project name (
flowtest
in this example)
and synthesis directory:
<Install Path>/verilog/example/synthesis
3.
Click OK to exit the dialog box and return to the project window.
Figure 5-5:
Create a New Project
