R
LogiCORE™PCI v3.0
Getting Started Guide
UG157 August 31, 2005
v3.0.151
Page 1: ...R LogiCORE PCI v3 0 Getting Started Guide UG157 August 31 2005 v3 0 151...
Page 2: ...THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR US...
Page 3: ...ument PDF Setup 02 06 03 3 4 Added paragraph formats GlossBulleted GlossNumbered and GlossNumberedCont 02 25 03 3 4 1 Minor clean ups and corrections 03 25 03 3 5 Corrected Reference Page identificati...
Page 4: ...PCI v3 0 151 Getting Started Guide www xilinx com UG157 August 31 2005...
Page 5: ...ng the Core 13 CORE Generator IP Updates Installer 14 Manual Installation CORE Generator IP Update 14 Direct Download of Standalone Core 15 Licensing Options 16 Evaluation 16 Full 16 Direct Download 1...
Page 6: ...om Chapter 5 Synthesizing a Design Synplicity Synplify 43 Verilog 43 VHDL 48 Exemplar LeonardoSpectrum 51 Xilinx XST 52 Chapter 6 Implementing a Design ISE Foundation 53 Chapter 7 Timing Simulation Ca...
Page 7: ...re provides information about installing and licensing the core Chapter 3 Family Specific Considerations provides information about design considerations specific to the PCI interface targeting Virtex...
Page 8: ...rt xilinx com xlnx xil_ans_browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Device specific informati...
Page 9: ...ecifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of ch...
Page 10: ...10 www xilinx com PCI v3 0 151 Getting Started Guide UG157 August 31 2005 Preface About This Guide R...
Page 11: ...gn includes a testbench capable of generating simple read and write transactions This stimulation generation capability is used to set up the configuration space of the design and then perform some si...
Page 12: ...designs that do not follow these guidelines Feedback Xilinx welcomes comments and suggestions about the PCI interface core and the documentation supplied with the core PCI Interface Core For comments...
Page 13: ...the product lounge System Requirements Windows Windows 2000 Professional Service Pack 2 4 Windows XP Home Service Pack 1 Windows XP Professional Service Pack 1 Solaris Linux Sun Solaris 8 9 Red Hat En...
Page 14: ...al Installation CORE Generator IP Update 1 Close the CORE Generator application if it is running 2 Download the IP Update ZIP file Windows or tar gz file UNIX from the following location and save it t...
Page 15: ...to the correct location For additional assistance installing the IP Update contact the Xilinx Hotline Direct Download of Standalone Core The PCI core can be downloaded from the Xilinx website and use...
Page 16: ...be downloaded from the core s lounge To create and download a license file for use with the CORE Generator do the following 1 After purchase you will receive a letter containing a serial number which...
Page 17: ...Installing Your License File R Installing Your License File After selecting a license option an email will be sent to you that includes instructions for installing your license file In addition infor...
Page 18: ...18 www xilinx com PCI v3 0 151 Getting Started Guide UG157 August 31 2005 Chapter 2 Installing and Licensing the Core R...
Page 19: ...files Table 3 1 Device and Interface Selection Table Supported Device Bus Type Wrapper File Constraints File Guide File 2S100 FG456 6C 33 MHz 5 0V 64 bit pcim_lc_33_5_s 2s100fg456_64_33 ucf no guide f...
Page 20: ...bit pcim_lc_33_3_s 2s200efg456_64_33 ucf no guide file 2S300E FG456 6C 33 MHz 3 3V 64 bit pcim_lc_33_3_s 2s300efg456_64_33 ucf no guide file 2S300E FG456 6C 66 MHz 3 3V 64 bit pcim_lc_66_3_d 2s300efg4...
Page 21: ...fg680_64_33 ucf no guide file V1000E FG680 6C 66 MHz 3 3V 64 bit pcim_lc_66_3_d v1000efg680_64_66 ucf v1000efg680_64_66 ncd V1000E FG680 6C 33 MHz 3 3V 64 bit pcim_lc_33_3_s v1000efg680_64_33 ucf no g...
Page 22: ..._66_3_s 2vp40ff1152_64_66 ucf 2vp40ff1152_64_66 ncd 2VP40 FF1152 5C I 33 MHz 3 3V 64 bit pcim_lc_33_3_s 2vp40ff1152_64_33 ucf no guide file 2VP50 FF1152 6C I 66 MHz 3 3V 64 bit pcim_lc_66_3_s 2vp50ff1...
Page 23: ...3V 64 bit pcim_lc_33_3_r 4vfx20ff672_64_33r ucf no guide file 4VLX25 FF668 11C I regional clock 66 MHz 3 3V 64 bit pcim_lc_66_3_r 4vlx25ff668_64_66r ucf no guide file 4VSX35 FF668 11C I regional clock...
Page 24: ...pcim_lc_33_3_s 2s200pq208_32_33 ucf no guide file 2S200 PQ208 5C 33 MHz 5 0V 32 bit pcim_lc_33_5_s 2s200pq208_32_33 ucf no guide file 2S200 PQ208 5C 33 MHz 3 3V 32 bit pcim_lc_33_3_s 2s150pq208_32_33...
Page 25: ...300ebg432_32_33 ucf no guide file V1000 FG680 5C 33 MHz 5 0 V 32 bit pcim_lc_33_5_s v1000fg680_32_33 ucf no guide file V1000 FG680 5C 33 MHz 3 3V 32 bit pcim_lc_33_3_s v1000fg680_32_33 ucf no guide fi...
Page 26: ...cf no guide file 4VSX35 FF668 10C I global clock 33 MHz 3 3V 32 bit pcim_lc_33_3_g 4vsx35ff668_32_33g ucf no guide file 4VFX20 FF672 10C I global clock 33 MHz 3 3V 32 bit pcim_lc_33_3_g 4vfx20ff672_32...
Page 27: ...ectory structure and file list 4VSX35 FF668 11C I regional clock 66 MHz 3 3V 32 bit pcim_lc_66_3r 4vsx35ff668_32_33r ucf no guide file 4VFX20 FF672 11C I regional clock 66 MHz 3 3V 32 bit pcim_lc_66_3...
Page 28: ...s Guide Files The guide files contain routing information required for high performance versions of the PCI interface Each guide file is specific to a particular device and PCI interface and must alwa...
Page 29: ...stribute reset signals because the global resource is not used The use of the global reset resource is not recommended Bus Width Detection A PCI interface that provides a 64 bit datapath needs to know...
Page 30: ...e and unprotected from roaming screwdrivers Datapath Output Clock Enable The PCI interface targeting Virtex devices uses one of the following methods to generate and distribute the datapath output clo...
Page 31: ...e clock from an I O pin This reference clock is distributed to all applicable IDELAYCTRL primitives using a global clock buffer It is important to note that there is some flexibility in the origin gen...
Page 32: ...losed system where the PCI bus clock is known to be a fixed frequency See Bus Clock Usage for additional information about the allowed behavior of the PCI bus clock in compliant systems Regional Clock...
Page 33: ...mum of 96 IOB that may be used for a PCI interface A 64 bit PCI interface requires 90 IOB and a 32 bit PCI interface requires 50 IOB In some device and package combinations typically physically large...
Page 34: ...communicates with the interface must also be synchronous to this clock It is important to note that the frequency of this clock is not guaranteed to be constant In fact in a compliant system the clock...
Page 35: ...e on Virtex Virtex 4 Virtex E Virtex II Virtex II Pro Spartan II Spartan IIE Spartan 3 and Spartan 3E devices With the exception of Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E these require VCCO t...
Page 36: ...r 3 3 volt signaling in Virtex II Pro Virtex 4 Spartan 3 and Spartan 3E devices the VCCO supply must be reduced to 3 0 volts and derived from a precision regulator This reduction of the output driver...
Page 37: ...apability item in user configuration space along with a dedicated PME output on a general purpose I O pin On all device families if the FPGA power is removed the general purpose I O pin will appear as...
Page 38: ...rations R This option is used to introduce additional delay on a global clock net It is important to note that this additional delay is observable on the CLK output of the PCI interface which is suppl...
Page 39: ...ng functional simulation ensure that the NC Verilog environment is properly configured 1 To start move into the functional simulation directory cd Install Path verilog example func_sim 2 Edit the ping...
Page 40: ...n files and exits The testbench prints status messages to the console After the simulation completes view the ncverilog log file to check for errors The Simvision browser may be used to view the simul...
Page 41: ...To run the simulation do modelsim do This compiles all modules loads them into the simulator displays the waveform viewer and runs the simulation VHDL 1 Navigate to the functional simulation directory...
Page 42: ...93 work simprim Xilinx Install Path vhdl src simprims simprim_Vcomponents_mti vhd vcom 93 work simprim Xilinx Install Path vhdl src simprims simprim_VITAL_mti vhd vlib unisim vcom 93 work unisim Xilin...
Page 43: ...ported synthesis tools include Synplicity Synplify v7 3 Exemplar LeonardoSpectrum v2003a Xilinx XST Synplicity Synplify Before attempting to synthesize a design ensure that the Synplicity Synplify env...
Page 44: ...files to the new project click Add The first file used by any design that instantiates Xilinx primitives is located in Synplicity Install Path lib xilinx 5 Navigate to the virtex v file then click Ad...
Page 45: ...files pci_lc_i v and pcim_lc v and click Add to move these files into the Files To Add list Ctrl click to select multiple files The final set of design files the user application is located in Instal...
Page 46: ...5 10 10 Click Change Result File to display the EDIF Result File dialog box then move the to following directory Install Path verilog example synthesis 11 Name the file pcim_top edf and click OK to s...
Page 47: ...ncy to 66 MHz 15 On the Implementation Results tab deselect Write Vendor Constraint File 16 Click OK to return to the main project window 17 From the main project window click Run Synplify synthesizes...
Page 48: ...select Project File and enter the project name flowtest in this example and synthesis directory Install Path vhdl example synthesis 3 Click OK to exit the dialog box and return to the project window...
Page 49: ...e Files To Add list The next files are located in Install Path vhdl src xpci 6 Navigate to the xpci directory select the simulation model and the wrapper files pci_lc_i vhd and pcim_lc vhd and click A...
Page 50: ...s by double clicking the flowtest vhdl folder if it is not already open Drag to reorder the source files in the hierarchical order shown in Figure 5 16 10 Click Change Result File to display the EDIF...
Page 51: ...ynthesis such as Compiling or Mapping are displayed When the process is complete Done is displayed Note that Synplify may issue a number of warnings which are expected about instantiated I O cells and...
Page 52: ...hierarchy preserve option prevents LeonardoSpectrum from dissolving the design hierarchy The chip option indicates that automatic I O buffer insertion should be performed 4 After synthesis is complete...
Page 53: ...vironment variables are set at the beginning of the script do not remove them The ngdbuild command lists both src xpci and synthesis as search directories The xpci directory contains a netlist of the...
Page 54: ...the placed and routed design 3 Implement the design by running the appropriate script During initial processing trials it is useful to enter commands one at a time from the command line rather than ru...
Page 55: ...configured for use In addition you must have successfully completed the implementation phase using the Xilinx tools 1 Navigate to the timing simulation directory and copy the back annotated timing mod...
Page 56: ...all Path verilog example post_sim cp xilinx pcim_top_routed v cp xilinx pcim_top_routed sdf 2 Edit the ping_tb f file This file lists command line arguments and is shown below source ping_tb v source...
Page 57: ...that the current directory is set to Install Path vhdl example post_sim 4 Create the simprim library This step is required only once the first time you perform a simulation vlib simprim vcom 93 work s...
Page 58: ...58 www xilinx com PCI v3 0 151 Getting Started Guide UG157 August 31 2005 Chapter 7 Timing Simulation R...
