Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
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UG155 March 24, 2008
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Appendix A
Core Verification, Compliance, and
Interoperability
Verification
The Ethernet 1000BASE-X PCS/PMA or SGMII core has been verified with extensive
simulation and hardware verification.
Simulation
A highly parameterizable transaction based test bench was used to test the core. Testing
included the following:
•
Register Access
•
Loss of Synchronization
•
Auto-Negotiation and error handling
•
Frame Transmission and error handling
•
Frame Reception and error handling
•
Clock Compensation in the Elastic Buffers
Hardware Verification
The core has been tested in a variety of hardware test platforms at Xilinx to represent
different parameterizations, including the following:
•
The core with RocketIO transceiver and performing the 1000BASE-X standard was
tested with the 1-Gigabit Ethernet MAC core from Xilinx.
This follows the architecture shown in
Figure 13-2
. A test platform was built around
these cores, including a back-end FIFO capable of performing a simple ping function,
and a test pattern generator. Software running on the embedded PowerPC was used to
provide access to all configuration and status registers. Version 3.0 of this core was
taken to the University of New Hampshire Interoperability Lab (UNH IOL) where
conformance and interoperability testing was performed.
•
The core with RocketIO transceiver (all supported families) and performing the
SGMII standard was tested with the Tri-speed Ethernet MAC core from Xilinx.
This was connected to an external PHY capable of performing 10BASE-T, 100BASE-T
and 1000BASE-T. The system was tested at all three speeds, following the architecture
shown in
Figure 13-7
and included the PowerPC based test platform.
