Xilinx DPU IP, Product Manual

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Chapter 2: Product Specification
DPU IP Product Guide www.xilinx.com 12
PG338 (v1.2) March 26, 2019
The DPU I/O signals are listed and described in Table 1.
Table 1: DPU Signal Description
Signal Name
Interface Type Width I/O Description
S_AXI Memory mapped
AXI slave interface 32 I/O 32-bit Memory mapped AXI interface
for registers.
s_axi_aclk Clock 1 I AXI clock input for S_AXI
s_axi_aresetn Reset 1 I Active-Low reset for S_AXI
dpu_2x_clk Clock 1 I Input clock used for DSP unit in DPU.
The frequency is two times of
m_axi_dpu_aclk.
dpu_2x_resetn Reset 1 I Active-Low reset for DSP unit
m_axi_dpu_aclk Clock 1 I Input clock used for DPU general logic.
m_axi_dpu_aresetn Reset 1 I Active-Low reset for DPU general logic
DPUx_M_AXI_INSTR Memory mapped
AXI master interface 32 I/O 32-bit Memory mapped AXI interface
for instruction of DPU.
DPUx_M_AXI_DATA0 Memory mapped
AXI master interface 128 I/O 128-bit Memory mapped AXI interface
for DPU data fetch.
DPUx_M_AXI_DATA1 Memory mapped
AXI master interface 128 I/O 128-bit Memory mapped AXI interface
for DPU data fetch.
dpu_interrupt Interrupt 1~3 O Active-High interrupt output from DPU.
The data width is decided by the DPU
number.
Notes:
1. If only input ports are needed, you can edit the ports in the block diagram and declare at the port
interface level.
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