DPU IP Product Guide
24
PG338 (v1.2) March 26, 2019
Chapter 4: Clocking and Resets
Introduction
There are three clock domains in the DPU IP: the register, the data controller, and the computation
unit. The three input clocks can be configured depending on the requirements. Therefore, the
corresponding reset for the three input clocks shall be configured correctly.
Clock Domain
Figure 12 shows the three clock domains.
PL
s_axi_clk
DPU
Register
Configure
Data Controller
Calculation Unit
m_axi_dpu_aclk
dpu_2x_aclk
X22334-022019
Figure 12: Clock Domain in DPU
Register Clock
The input
s_axi_clk
is used for the register configure module. This module receives the DPU configure
data though the S_AXI interface and the related clock of S_AXI is
s_axi_clk
. The register for DPU
configure is updated at a very low frequency and most of those registers are configured at the start of a
task. Xilinx® recommends that the frequency of the
s_axi_clk
is set as 100 MHz.
