Chapter 2: Product Specification
DPU IP Product Guide
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PG338 (v1.2) March 26, 2019
Interrupts
Upon the completion of one DPU task, an interrupt from DPU occurs to signal the completion of the
task. The active-High of the Reg_dpu0_start means the start of a DPU task for DPU core0. At the end of
the DPU task, DPU sends an interrupt and one bit in the register Reg_dpu_isr is set to 1. The position of
the active bit in the Reg_dpu_isr depends on the number of DPU cores. For example, when the DPU
core1 finishes a task while the DPU core 0 is still working, the Reg_dpu_isr is set as 2, the lowest bit is 0,
and the lower bit is 1.
The data width of dpu_interrupt is determined by the number of DPU cores. When the parameter of
DPU_NUM is set to 2, it means the DPU IP is integrated with two DPU cores, and the data width of the
dpu_interrupt signal is two bits. The lower bit represents the DPU core 0 interrupt and the higher bit
represents the DPU core1 interrupt.
The interrupt connection between the DPU and PS is described in the Device Tree file, which indicates
the interrupt number of DPU connected to the PS. The reference connection is shown as Figure 9.
Figure 9: Reference Connection for DPU Interrupt
Notes:
1.
If DPU is working with the DNNDK package, you should connect the dpu_interrupt at the 10th bit in
the irq signal of PS. For example, if the DPU_NUM is set as 2, the 2-bit dpu_interrupt should connect
with irq10 and irq11 of PS.
2.
irq7~irq0 corresponds to pl_ps_irq0[7:0].
3.
irq15~irq8 corresponds to pl_ps_irq1[7:0].
