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Xilinx AC701 Si5324, Design Manual

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Xilinx AC701 Si5324 Design Manual Download Page 7

AC701 Setup 

Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) 

connector on the AC701 board 

– Connect this cable to your PC 
– Power on the AC701 board 

Summary of Contents for AC701 Si5324

Page 1: ...November 2014 AC701 Si5324 Design XTP231 ...

Page 2: ...rs contained in the Information or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE INFORMATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR P...

Page 3: ...Overview Xilinx AC701 Board Software Requirements AC701 Setup Reducing Jitter with the Si5324 Compile AC701 Si5324 Design References Note This presentation applies to the AC701 ...

Page 4: ...trates the relative differences of a Jitter Attenuator device in Bypass mode or in PLL mode Neither the Evaluation board nor the design are for characterization purposes Please see the Silicon Labs web site for Jitter Attenuator device data Reference Design Source AC701 Si5324 Design Files 2014 4 C ZIP file Available through http www xilinx com ac701 Note Presentation applies to the AC701 ...

Page 5: ...Xilinx AC701 Board ...

Page 6: ...Vivado Software Requirements Xilinx Vivado Design Suite 2014 4 Design Edition Note Presentation applies to the AC701 ...

Page 7: ...AC701 Setup Connect a USB Type A to Micro B cable to the USB JTAG Digilent connector on the AC701 board Connect this cable to your PC Power on the AC701 board ...

Page 8: ...AC701 Si5324 Setup Unzip the AC701 Si5324 Design Files 2014 4 C ZIP file Available through http www xilinx com ac701 Note Presentation applies to the AC701 ...

Page 9: ...Reducing Jitter with the Si5324 ...

Page 10: ...Reducing Jitter with the Si5324 A means of measuring jitter is required for this section A LeCroy 816Zi A Scope was used stock photo shown Note Presentation applies to the AC701 ...

Page 11: ...Reducing Jitter with the Si5324 Connect SMA cables to J33 and J34 USER_GPIO_P N Connect these cable to your oscilloscope ...

Page 12: ...Reducing Jitter with the Si5324 Open a Vivado Tcl Shell Start All Programs Xilinx Design Tools Vivado 2014 4 Vivado 2014 4 Tcl Shell Note Presentation applies to the AC701 ...

Page 13: ...ducing Jitter with the Si5324 Download the bypass bitstream with Vivado In the Vivado Tcl Shell type cd C ac701_si5324 ready_for_download source bypass_download tcl Note Presentation applies to the AC701 ...

Page 14: ...Reducing Jitter with the Si5324 LeCroy Oscilloscope setup Press the Default Setup followed by the Auto Setup twice ...

Page 15: ...Reducing Jitter with the Si5324 Adjust the Horizontal knob until you have 5 μs div ...

Page 16: ...Reducing Jitter with the Si5324 From the LeCroy scope menu select Analysis Serial Data ...

Page 17: ...Reducing Jitter with the Si5324 Select Quick View ...

Page 18: ...Reducing Jitter with the Si5324 Set the inputs to Input1 Input2 and the Data to match your setup and click OK ...

Page 19: ...Reducing Jitter with the Si5324 Click the Close button ...

Page 20: ...Reducing Jitter with the Si5324 Note that the DCD Duty Cycle Distortion is 53 6 ps ...

Page 21: ...Reducing Jitter with the Si5324 Download the enabled bitstream with Vivado In the Vivado Tcl Shell type source enabled_download tcl Note Presentation applies to the AC701 ...

Page 22: ...Reducing Jitter with the Si5324 Note that the DCD Duty Cycle Distortion is 4 0 ps Including the Si5324 Jitter Attenuator PLL in the clock path reduces DCD ...

Page 23: ...Compile AC701 Si5324 Design ...

Page 24: ...Compile AC701 Si5324 Design Open Vivado Start All Programs Xilinx Design Tools Vivado 2014 4 Vivado Select Open Project Note Presentation applies to the AC701 ...

Page 25: ...Compile AC701 Si5324 Design Open the AC701 Design Design Name ac701_si5324 xpr Note Presentation applies to the AC701 ...

Page 26: ...pile AC701 Si5324 Design The design is fully implemented you can recompile or export to SDK To recompile right click synth_1 select Reset Runs then Generate Bitstream Note Presentation applies to the AC701 ...

Page 27: ...Compile AC701 Si5324 Design Once done both the Synthesis and Implementation will have green check marks Note Presentation applies to the AC701 ...

Page 28: ...Compile AC701 Si5324 Design The BIST Design has been implemented with IP Integrator IPI Click Open Block Design Note Presentation applies to the AC701 ...

Page 29: ...Compile AC701 Si5324 Design All the IP Blocks used in the design can be seen in this view Click Open Implemented Design Note Presentation applies to the AC701 ...

Page 30: ...Compile AC701 Si5324 Design View Implemented Design Note Presentation applies to the AC701 ...

Page 31: ...Compile AC701 Si5324 Design Select File Export Export Hardware Click OK Note Presentation applies to the AC701 ...

Page 32: ...Compile AC701 Si5324 Design Select File Launch SDK Click OK Note Presentation applies to the AC701 ...

Page 33: ...Compile AC701 Software in SDK SDK Software Compile Build ELF files in SDK Note Presentation applies to the AC701 ...

Page 34: ...Program AC701 with Si5324 Design ...

Page 35: ...with the Si5324 Application ELF Update the bitstream download bit with the Si5324 Application ELF Cycle power on the AC701 to clear out any previous settings in the Si5324 Select Xilinx Tools Program FPGA 1 1 Note Presentation applies to the AC701 ...

Page 36: ...Program AC701 with Si5324 Design Init memory with the Si5324 Application ELF Select hello_iic_5324 elf 1 Click Program Note Presentation applies to the AC701 1 ...

Page 37: ...Program AC701 with Si5324 Design Note that the DCD Duty Cycle Distortion has a low value now ...

Page 38: ...C701 with Si5324 Design To set the Si5324 for Bypass mode edit the hello_iic_si5324 c Locate the line Change to 1 to set Si5324 into Bypass PLL mode Change the if 0 to if 1 Note Presentation applies to the AC701 ...

Page 39: ...h Si5324 Design To set the Si5324 for Bypass mode edit the hello_iic_si5324 c Scroll down and locate the line Change to 1 to set Si5324 Loop Bandwidth BWSEL Change the if 1 to if 0 Note Presentation applies to the AC701 ...

Page 40: ...Program AC701 with Si5324 Design Recompile the ELF file Select the hello_iic_5324 project and press F5 to rebuild Note Presentation applies to the AC701 ...

Page 41: ...with the Si5324 Application ELF Update the bitstream download bit with the Si5324 Application ELF Cycle power on the AC701 to clear out any previous settings in the Si5324 Select Xilinx Tools Program FPGA 1 1 Note Presentation applies to the AC701 ...

Page 42: ...Program AC701 with Si5324 Design Init memory with the Si5324 Application ELF Select hello_iic_5324 elf 1 Click Program Note Presentation applies to the AC701 1 ...

Page 43: ...Program AC701 with Si5324 Design Note that the DCD Duty Cycle Distortion is now higher ...

Page 44: ...References ...

Page 45: ...labs com Support 20Documents TechnicalDocs Si5324 pdf Vivado Programming and Debugging Vivado Design Suite Programming and Debugging User Guide UG908 http www xilinx com support documentation sw_manuals xilinx2014_4 ug908 vivado programming debugging pdf ...

Page 46: ...Documentation ...

Page 47: ...pport answers 51456 htm AC701 Documentation Artix 7 FPGA AC701 Evaluation Kit http www xilinx com products boards and kits EK A7 AC701 G htm AC701 Getting Started Guide http www xilinx com support documentation boards_and_kits ac701 2014_1 ug967 ac701 eval kit getting started pdf AC701 User Guide http www xilinx com support documentation boards_and_kits ac701 ug952 ac701 a7 eval bd pdf ...

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