Program AC701 with Si5324 Design
Init memory with the Si5324 Application ELF
– Update the bitstream (download.bit) with the Si5324 Application ELF
– Cycle power on the AC701 to clear out any previous settings in the Si5324
– Select Xilinx Tools
→
Program FPGA (1)
1
Note:
Presentation applies to the AC701
Summary of Contents for AC701 Si5324
Page 1: ...November 2014 AC701 Si5324 Design XTP231 ...
Page 5: ...Xilinx AC701 Board ...
Page 9: ...Reducing Jitter with the Si5324 ...
Page 15: ...Reducing Jitter with the Si5324 Adjust the Horizontal knob until you have 5 μs div ...
Page 16: ...Reducing Jitter with the Si5324 From the LeCroy scope menu select Analysis Serial Data ...
Page 17: ...Reducing Jitter with the Si5324 Select Quick View ...
Page 19: ...Reducing Jitter with the Si5324 Click the Close button ...
Page 20: ...Reducing Jitter with the Si5324 Note that the DCD Duty Cycle Distortion is 53 6 ps ...
Page 23: ...Compile AC701 Si5324 Design ...
Page 30: ...Compile AC701 Si5324 Design View Implemented Design Note Presentation applies to the AC701 ...
Page 34: ...Program AC701 with Si5324 Design ...
Page 37: ...Program AC701 with Si5324 Design Note that the DCD Duty Cycle Distortion has a low value now ...
Page 43: ...Program AC701 with Si5324 Design Note that the DCD Duty Cycle Distortion is now higher ...
Page 44: ...References ...
Page 46: ...Documentation ...
