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0x0001 Bit 0
RunEna
Set to 1 to start data acquisition or 0 to stop.
Automatically cleared when DSP de-asserts Active to end
run.
0x0002 Bit 1
Unused
Reserved for future use.
0x0004 Bit 2
PCIactive
Set to reserve external memory I/O for host
0x0008 Bit 3
Unused
Reserved for future use.
0x0010 Bit 4
DSPReset
Write only.
Set to reset DSP processor to initiate program download
0x0020 Bit 5
SynchCtrl
Read only. If low, module is busy with run initialization,
has filled its I/O buffer with data, or is finished with the
run.
0x0040 Bit 6
Unused
Reserved for future use.
0x0080 Bit 7
Unused
Reserved for future use.
0x0100 Bit 8
SynchFlag Read only. Reserved for future use.
0x0200 Bit 9
Live*
Read only. If zero, DSP is taking data.
0x0400 Bit 10
Unused
Reserved for future use.
0x0800 Bit 11
Unused
Reserved for future use.
0x1000 Bit 12
Unused
Reserved for future use.
0x2000 Bit 13
Active
Read only. If set, there is a run in progress.
0x4000 Bit 14
LAMState Read only. If set, LAM is set internally.
0x8000 Bit 15
Unused
Reserved for future use.