
Figure 10.1. Simplified input stage of Pixie-4 showing jumpers, input termination and
attenuation, and the overvoltage protection circuit.
10.2 Clock Jumpers
Table 10.2: On-board jumper settings for the clock distribution on Pixie-4 modules.
Clock mode
JP1 and JP2
JP3
PCB Label
Single Module
Connect pins 2 and 3 of JP2
not set
LOC to IN
Daisy-Chained
Clock Master
Connect pins 2 and 3 of JP2
not set
LOC to IN
Daisy-Chained
Clock Repeater
Not set
set
Left
Bussed Clock
Master
Connect pins 2 and 3 of JP2
Connect pin1, JP1 to pin 1, JP2
not set
LOC to IN
OUT to BUS
Bussed Clock
Slave
Connect pins 1 and 2 of JP2
not set
BUS to IN
Clock Slave with
PXI clock
Connect pin2, JP1 to pin 2, JP2 not set
PXI to IN
Clock Master for
PXI clock
(Revision C only)
Connect pin2, JP1 to pin 2, JP2
Connect pin3, JP1 to pin 3, JP2
not set
PXI to IN
LOC to BP