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RV2 is connected as a variable resistor and consequently controls the amplitude of the
modulation signal to both oscillators; RV2 therefore sets the overall frequency deviation of
the transmitter.
RV3 controls the amplitude of the modulation signal to only the UHF oscillator. This
arrangement constitutes ‘dual-point modulation’; the modulation applied to the UHF
oscillator is only effective outside the bandwidth of the frequency control loop while that
applied to the TCXO is effective within this bandwidth. RV3 thus functions as a ‘deviation
balance’ control and is adjusted such that the overall modulation response is flat across its
full frequency range.
R28 is provided so that there is no significant change in the DC level fed to the modulation
input of the TCXO as RV2 is adjusted. (A DC shift would cause a corresponding shift in
the transmitter frequency.) In contrast, the DC voltage fed to the modulation input of the
UHF oscillator is allowed to change as RV3 is adjusted since this has no effect on the
mean transmitter frequency.
3.4 RADIO FREQUENCY STAGE
TR5 acts as a UHF oscillator whose frequency is determined primarily by L8, D3, D4 and
trimmer C32. D3 and D4 are varicap diodes and allow the oscillator to be tuned by means
of a DC voltage which is fed to the diodes via L9. Trimmer C32 provides coarse tuning of
the oscillator frequency.
Varicap diode D2 is also loosely coupled into the oscillator circuit via C26 and provides a
means of frequency-modulating the oscillator.
The output from the oscillator is developed across R42 at the collector of TR5 and is fed
via C40 to buffer amplifier IC5. This amplifier provides an increased output level while
isolating the oscillator from the rest of the circuit. The output from IC5 is fed through a
low-pass filter (C45, L12 and C48); the output from this filter is fed to the input of the
frequency synthesiser IC6 and also to buffer amplifier IC7.
Frequency synthesiser IC6 incorporates two programmable frequency dividers and an
edge-triggered phase comparator which is driven by the outputs of the two frequency
dividers. The division ratios are controlled by means of serial data generated by
microprocessor IC3. The filtered output from buffer amplifier IC5 is fed via C47 to the
input of one of the frequency divders at pin 8; the other input at pin 1 is driven by the
output of TCXO U1 via C28 and R33. The TCXO provides a reference frequency which is
very stable across the operating temperature range of the transmitter.
The phase comparator output from IC6 appears at pin 5 and is fed via R44 and R41 to L9
in the UHF oscillator. This completes the control loop and IC6 is thus able to control the
frequency of the UHF oscillator. R47 and C44 determine the dynamic behaviour of the
Summary of Contents for ST500
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