Customer Information
WM9081-6222-CO28-M-REV2
w
May 2009, Rev 1.0
Customer Information
7
REGISTER SETTINGS
Register settings provided below are simply the minimum requirement to configure the desired path
and have not in any way been optimised.
REG
INDEX
DATA
VALUE COMMENT
0x00
0x9081
Reset
0x0E 0x4001
Clock Control 3(0EH): 4001 CLK_SRC_SEL=0, CLK_OP_ENA=0,
CLK_TO_ENA=0, CLK_DSP_ENA=0, CLK_SYS_ENA=1
0x26 0x8100
Write Sequencer 1(26H): 8100 WSEQ_ENA=1, WSEQ_ABORT=0,
WSEQ_START=1, WSEQ_START_INDEX=000_0000 (SEQUENCE 1)
PERFORMANCE PLOT
Audio Precision
05/15/09 10:42:10
WM9081 -- DAC --> CLASS D -- THD+N v Amplitude
Color
Sweep
Trace
Line Style
Thick
Data
Axis
Comment
1
1
Red
Solid
2
Anlr.THD+N Ampl
Left
A-weight
2
1
Blue
Solid
2
Anlr.THD+N Ampl
Left
AES17
System AP2
Board: 6222-EV1-REV1 + WM9081-6222-CO28-M-REV2
Device Date Code: WPF
Input Path: SPDIF_IN
Input Signal: 997Hz; 24-bit; 256fs (fs =48kHz)
Output Path: SPKOUT (4R1 + 10uH Load)
Output Reference: 0dBrA = +8.875 dBV
Supplies: AVDD=DBVDD=DCVDD=+3.3V, 5.0V
BW filter : AUX0025, 22Hz-22kHz
Additional Filtering: as stated
Dither: None
RMS or Averaging: Averaging
-100
-30
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
d
B
r
A
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBFS
Notes:
1. The WM9081-6222-CO28-M-REV2 contains a low-pass filter, which can be used to filter the
Class D output signal for monitoring purposes. The filtered output can be observed on J8 (6222-
EV1-REV1) when SP2 and SP3 (6222-EV1-REV1) are shorted. When a suitable loudspeaker
load is used, the on-board low-pass filter is not required.
2. For efficiency and power consumption measurements of the class D output, it is recommended
to leave SP2 and SP3 (6222-EV1-REV1) open to avoid quiescent power consumption in the RC
filter.
