Customer Information
WM9081-6222-CO28-M-REV2
w
May 2009, Rev 1.0
Customer Information
13
REGISTER SETTINGS
Register settings provided below are simply the minimum requirement to configure the desired path
and have not in any way been optimised.
REG
INDEX
DATA
VALUE COMMENT
0x00
0x9081
Reset
0x03 0x0039
Analogue Speaker PGA(03H): 0039 SPKPGA_MUTE=0,
SPKPGAZC=0, SPKPGA_VOL=11_1001
0x04 0x0023
VMID Control(04H): 0023 VMID_BUF_ENA=1, VMID_RAMP=0,
VMID_SEL=01, VMID_FAST_ST=1
0x05 0x002A
Bias Control 1(05H): 002B BIAS_SRC=0, STBY_BIAS_LVL=1,
STBY_BIAS_ENA=0, BIAS_LVL=10, BIAS_ENA=1,
STARTUP_BIAS_ENA=0
0x07 0x0001
Analogue Mixer(07H): 0001 DAC_SEL=0, IN2_VOL=0, IN2_ENA=0,
IN1_VOL=0, IN1_ENA=1
0x08 0x0001
Anti Pop Control(08H): 0001 LINEOUT_DISCH=0, LINEOUT_VROI=0,
LINEOUT_CLAMP=1
0x0B 0x0186
Power Management(0BH): 0186 TSHUT_ENA=1, TSENSE_ENA=1,
TEMP_SHUT=0, LINEOUT_ENA=0, SPKPGA_ENA=1, SPK_ENA=1,
DAC_ENA=0
0x0E 0x4003
Clock Control 3(0EH): 4003 CLK_SRC_SEL=0, CLK_OP_ENA=0,
CLK_TO_ENA=0, CLK_DSP_ENA=1, CLK_SYS_ENA=1
PERFORMANCE PLOT
Audio Precision
WM9081 -- IN1 --> CLASS D -- THD+N v Amplitude
Color
Sweep
Trace
Line Style
Thick
Data
Axis
Comment
1
1
Red
Solid
2
Anlr.THD+N Ampl
Left
A-weight
2
1
Blue
Solid
2
Anlr.THD+N Ampl
Left
AES17
System AP2
Board: 6222-EV1-REV1 + WM9081-6222-CO28-M-REV2
Device Date Code: WPF
Input Path: IN1
Input Signal: 997Hz
Output Path: SPKOUT (4R1 + 10uH Load)
Output Reference: 0dBrA = +8.839dBV
Supplies: AVDD=DBVDD=DCVDD=+3.3V, 5.0V
BW filter : 22Hz-22kHz
Additional Filtering: as stated
Dither: None
RMS or Averaging: Averaging
-100
-30
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
d
B
r
A
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBV
