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Wolfson WM894 -6229-CS36-M-REV1 Series, Manual

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Wolfson WM894 -6229-CS36-M-REV1 Series Manual Download Page 8

WM894x-6229-CS36-M-REV1

 Customer 

Information

  

 

w 

August 2009, Rev 1.0 

Customer Information

 

8

 

 

WM8945 and WM8944 Devices 

REG 

INDEX 

(HEX) 

DATA 

VALUE 

(HEX) COMMENT 

0x00 0x0000 Reset 
0x02 

0x000D 

Enable Master Bias and VMID buffer. 

0x07 

0x001D 

Enable VMID, set sample rate to 48kHz. 

0x35 0x8007 Enable 

LDO. 

0x31 

0x0008 

LINEOUT L Mixer selects DACL to LINEOUTL. 

0x03 

0x4331 

Enable LINEOUTL and Left DAC. 

0x15 0x0010 Enable 

DAC 

Auto-mute 

0x08 0x0101 MCLK=12.288MHz, 

SYSCLK=24.576MHz 

0x2A 0x8400 

Enable VMID for LINEOUT output stage and un-mute 
LINEOUT.  

0x40 

0x0001 

Select DSP Playback. 

0x06 

0x0306 

FLL clock, enable SYSCLK. 

 

 

PERFORMANCE PLOT 

DBVDD =LDOVDD=SPKVDD=3.3V; DCVDD=1.8V 

Sample Frequency=48kHz 

 

THD+N v Amplitude (A-weighted) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Summary of Contents for WM894 -6229-CS36-M-REV1 Series

Page 1: ...SPKOUT 8R BTL IN1L IN1R to ADC IN1L IN2L IN1R IN2R to ADC Diff AUX1 AUX2 to ADC Video Buffer This document should be used as a starting point for evaluation of WM8944 WM8945 WM8946 WM8948 CODECs but...

Page 2: ...F CONTENTS 2 BOARD CONFIGURATION STAND ALONE 3 CONNECTION DIAGRAM 3 I O TABLE 5 BOARD CONFIGURATION WITH 6229 EV1 MAIN BOARD 6 DAC TO LINEOUTL AND LINEOUTR 6 DAC TO SPKOUTR 8R BTL 9 IN1L IN1R TO ADC 1...

Page 3: ...ted headers This section will detail important considerations and provide all information required to do this without risking damage to the device CONNECTION DIAGRAM Figure 1 to 4 below shows the conn...

Page 4: ...WM894x 6229 CS36 M REV1 Customer Information w August 2009 Rev 1 0 Customer Information 4 Figure 3 WM8945 Stand Alone Board Configuration Figure 4 WM8944 Stand Alone Board Configuration...

Page 5: ...RCLK H3 pin 8 Audio interface left right clock DACDAT H3 pin 4 DAC digital audio data ADCDAT H3 pin 6 ADC Digital Microphone digital audio data Analogue Inputs IN1L DMICDAT H2 pin 14 Left input 1 Digi...

Page 6: ...29 CS36 M REV1 Customer Mini Board in combination with the 6229 EV1 main board This system is the reference platform for measurement data contained in this document Please note that only a limited num...

Page 7: ...ATA VALUE HEX COMMENT 0x00 0x0000 Reset 0x02 0x000D Enable Master Bias and VMID buffer 0x07 0x001D Enable VMID set sample rate to 48kHz 0x35 0x8007 Enable LDO 0x31 0x0008 LINEOUT L Mixer selects DACL...

Page 8: ...e rate to 48kHz 0x35 0x8007 Enable LDO 0x31 0x0008 LINEOUT L Mixer selects DACL to LINEOUTL 0x03 0x4331 Enable LINEOUTL and Left DAC 0x15 0x0010 Enable DAC Auto mute 0x08 0x0101 MCLK 12 288MHz SYSCLK...

Page 9: ...29 CS36 M REV1 w August 2009 Rev 1 0 Customer Information 9 DAC TO SPKOUTR 8R BTL The following section details board configuration for DAC to SPKOUTL and SPKOUTR driving an 8 Bridge tied load BTL BLO...

Page 10: ...0x07 0x001D Enable VMID set sample rate to 48kHz 0x35 0x8007 Enable LDO 0x2B 0x0088 SPKOUTL Mixer selects DACL to SPKOUTL Output Mixer selects PGA to SPKL 0x2C 0x00A0 SPKOUT R Mixer selects DACR to S...

Page 11: ...n WM894x 6229 CS36 M REV1 w August 2009 Rev 1 0 Customer Information 11 IN1L IN1R TO ADC The following section details board configuration for IN1L and IN1R inputs connected to the ADC BLOCK DIAGRAM B...

Page 12: ...L 0x29 0x0010 Un mute PGAR 0x19 0x0000 Un mute ADCs 0x08 0x0101 MCLK 12 288MHz PLL set for 24 576MHz Output 0x07 0x001D Enable VMID set sample rate to 48kHz 0x06 0x0306 Enable SYSCLK FLL clock put dig...

Page 13: ...Customer Information WM894x 6229 CS36 M REV1 w August 2009 Rev 1 0 Customer Information 13 PERFORMANCE PLOT DBVDD LDOVDD SPKVDD 3 3V DCVDD 1 8V Sample Frequency 48kHz THD N v Amplitude A weighted...

Page 14: ...R TO ADC DIFF The following section details board configuration for IN1L DMICDAT IN2L and IN1R IN2R connected as differential signals to the ADC BLOCK DIAGRAM DCVDD DBVDD SPKVDD CS GPIO2 SCLK SDA CIFM...

Page 15: ...and WM8946 Devices REG INDEX DATA VALUE COMMENT 0x00 0x0000 Reset 0x02 0x3C0D Enable Input PGAs ADCs Master Bias and VMID buffer 0x35 0x8007 Enable LDO 0x27 0x0035 Configure PGA Source to select diffe...

Page 16: ...0x35 0x8007 Enable LDO 0x27 0x0035 Configure PGAL Source to select differential inputs 0x28 0x0010 Un mute PGAL 0x19 0x0000 Un mute ADCL 0x08 0x0101 MCLK 12 288MHz PLL set for 24 576MHz Output 0x07 0...

Page 17: ...UX1 AUX2 TO AUXADC The following section details board configuration for AUX1 and AUX2 inputs to the AUXADC BLOCK DIAGRAM DCVDD DBVDD SPKVDD CS GPIO2 SCLK SDA CIFMODE GPIO3 MCLK SDOUT GPIO4 GPIO1 DACD...

Page 18: ...Manual 0x3E 0x0001 Measure AUX1 Example 1 Configure the AUX1 Measurement for Manual Polling WM8946 and WM8944 Devices REG INDEX HEX DATA VALUE HEX COMMENT 0x00 0x0000 Reset 0x02 0x000D Enable Master...

Page 19: ...omer Information WM894x 6229 CS36 M REV1 w August 2009 Rev 1 0 Customer Information 19 VIDEO BUFFER The following section details board configuration of the Video Buffer BLOCK DIAGRAM BOARD CONFIGURAT...

Page 20: ...any way been optimised REG INDEX HEX DATA VALUE HEX COMMENT 0x00 0x0000 Reset 0x02 0x000D Enable Master Bias and VMID buffer 0x07 0x001D Enable VMID 0x26 0x00A0 Enable Video Buffer with 6dB Gain and e...

Page 21: ...lease contact the Wolfson Microelectronics Applications group through the following channels Email apps wolfsonmicro com Telephone Apps 44 0 131 272 7070 Fax 44 0 131 272 7001 Mail Applications Engine...

Page 22: ...ar systems or systems where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes i...

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