WM894x-6229-CS36-M-REV1
Customer
Information
w
August 2009, Rev 1.0
Customer Information
10
Add shorting links to J36, J41 to bypass the output coupling capacitors and J45 connect an 8
Ω
load
across the SPK outputs.
REGISTER SETTINGS
Register settings provided below are simply the minimum requirement to configure the desired path
and have not in any way been optimised.
REG
INDEX
DATA
VALUE COMMENT
0x00 0x0000 Reset
0x02
0x000D
Enable Master Bias and VMID buffer.
0x07
0x001D
Enable VMID, set sample rate to 48kHz.
0x35 0x8007 Enable
LDO.
0x2B 0x0088
SPKOUTL Mixer selects DACL to SPKOUTL, Output
Mixer selects PGA to SPKL.
0x2C 0x00A0 SPKOUT R Mixer selects DACR to SPKOUTR, Output
Mixer selects PGA to SPKR.
0x2F
0x0139
Unmute Left speaker PGA
0x30
0x0139
Unmute Right speaker PGA
0x03
0xFCCF
Enable SPKOUT, SPKOUT Mixers and DACs.
0x15 0x0010 Enable
DAC
Auto-mute
0x08 0x0101 MCLK=12.288MHz,
SYSCLK=24.576MHz
0x2A
0xB000
Enable VMID for SPKOUT output stage.
0x40
0x0001
Select DSP Playback.
0x06
0x0306
FLL clock, enable SYSCLK.
PERFORMANCE PLOT
DBVDD =LDOVDD=SPKVDD=3.3V; DCVDD=1.8V
Sample Frequency=48kHz
THD+N v Amplitude (A-weighted)
