W7500x Reference Manual Version1.1.0
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Receive status can also be read from the UART1RSR register.
A write to the UART1ECR register clears the framing, parity, break, and overrun errors.
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res
res
res
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res
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res
res
res
res
res
res
res
res
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1
0
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res
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res
res
res
res
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res
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res
OE
BE
PE
FE
[3] OE – Overrun error
This bit is set to 1 if data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UART1ECR
[2] BE – Break error
This bit is cleared to 0 by a write to UART1ECR
[1] PE – Parity error
When set to 1, it indicates that the parity of the received data character does not
match
the parity that the EPS and SPS bits in the line control register, UARTLCR_H select
This bit is cleared to 0 by a write to UART1ECR
[0] FE – Framing error
When set to 1, in indicates that the received character didn’t have a valid stop bit
This bit is cleared to 0 by a write to UART1ECR
UART1FR (UART1 Flag Register)
Address offset: 0x0018
Reset value: 0bx11000xxx
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RI
TXFE
RXFF
TXFF
RXFE BUSY
DCD
DSR
CTS
R
R
R
R
R
R
R
R
R
[8] RI – Ring indicator
This bit is the complement of the UART ring indicator, UART1RI.
1: When nUART1RI is LOW