PCM-MIO-A-1/Software Summary
v1.0
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Page 23
Notes:
(1) Accessed when READBACK ENABLE (BASE +15 bit 4) = 1
(2) Accessed when REGISTER SELECT (BASE +15 bit 3) = 0
(3) Accessed when REGISTER SELECT (BASE +15 bit 3) = 1
(4) 0=Disabled, 1=Enabled
(5) Accessed when D/A2 SELECT (BASE + 15 bit 5) = 0
(6) Accessed when D/A2 SELECT (BASE + 15 bit 5) = 1
The Linear Technology LTC-2704 devices are unique in that each channel
consists of a double-buffered data register (B1 Code and B2 Code) and a
double-buffered span register (B1 Span and B2 Span). B1 buffers are the
holding buffers and data is loaded into each one using a write operation,
the DAC outputs are not affected. The contents of the B2 buffers can only
be updated by copying the contents of B1 into B2 via an update operation
initiated by the Command Code. The contents of the B2 buffers (both DAC
Span and DAC Code) directly control the DAC output voltage or the DAC
output range. Configuration, programming and writing of the D/A data is
achieved through a series of control registers listed below for each DAC.
8.2.3 Command Register
Each DAC contains a command register used to configure the span and
load the data. The command word consists of a 4-bit command and a 4-bit
address, as shown. Each DAC contains a command register used to
Register Address
(Base+)
Read/
Write
7
6
5
4
3
2
1
0
DATA_LO
12
R/W
LOW ORDER DATA BYTE
DATA-BIT 7
DATA-BIT 6
DATA-BIT 5
DATA-BIT 4
DATA-BIT 3
DATA-BIT 2
DATA-BIT 1
DATA-BIT 0
READBACK
(1)
12
R
LOW ORDER DATA BYTE
DATA-BIT 7
DATA-BIT 6
DATA-BIT 5
DATA-BIT 4
DATA-BIT 3
DATA-BIT 2
DATA-BIT 1
DATA-BIT 0
DATA_HI
13
R/W
HIGH ORDER DATA BYTE
DATA-BIT 15 DATA-BIT 14 DATA-BIT 13 DATA-BIT 12 DATA-BIT 11 DATA-BIT 10 DATA-BIT 9
DATA-BIT 8
READBACK
(1)
13
R
HIGH ORDER DATA BYTE
DATA-BIT 15 DATA-BIT 14 DATA-BIT 13 DATA-BIT 12 DATA-BIT 11 DATA-BIT 10 DATA-BIT 9
DATA-BIT 8
COMMAND
(2)
14
R/W
COMMAND
CMD-BIT 7
CMD-BIT 6
CMD-BIT 5
CMD-BIT 4
CMD-BIT 3
CMD-BIT 2
CMD-BIT 1
CMD-BIT 0
RESOURCE
(3)
14
R/W
DON’T CARE
INTERRUPT ROUTING ASSIGNMENT
IRQ[15-3] 0, 1, 2, 8, AND 13 NOT AVAILABLE
X
X
X
X
BIT 3
BIT 2
BIT 1
BIT 0
RESOURCE
ENABLE
15
W
X
X
D/A2
SELECT
READBACK
ENABLE
REGISTER
SELECT
X
X
INTERRUPT
ENABLE (4)
STATUS (5)
15
R
DATA READY
X
X
INTERRUPT
REQUEST
PENDING (4)
REGISTER
SELECT
STATUS
X
X
INTERRUPT
ENABLE BIT
STATUS (4)
IRQ
REGISTER
(6)
15
R
X
X
DA/2 IRQ
PENDING
DIO IRQ
PENDING
DA/1 IRQ
PENDING
AD/2 IRQ
PENDING
AD/1 IRQ
PENDING
