PCM-MIO-A-1/Software Summary
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determine which device generated an interrupt request is to utilize the
Master Interrupt Status Register.
8.2
D/A Converters
The PCM-MIO-A-1 contains two Linear Technology LTC-2704 digital-to-
analog converter (DAC) devices. Each device is a 4-channel converter with
software selectable output span.
8.2.1 D/A1 - Starting at BASE +8
The COMMAND register, RESOURCE register and RESOURCE ENABLE
registers are used to configure the D/A device operation. The specific
options of each register are detailed here.
Notes:
(1) Accessed when READBACK ENABLE (BASE +11 bit 4) = 1
(2) Accessed when REGISTER SELECT (BASE +11 bit 3) = 0
(3) Accessed when REGISTER SELECT (BASE +11 bit 3) = 1
(4) 0=Disabled, 1=Enabled
8.2.2 D/A2 - Starting at BASE +12
As shown in the table below, interface to the second device is almost
identical to the first with a change in the base address.
The RESOURCE ENABLE register does contain an additional register select
bit, MASTER IRQ / DA2 SELECT. If this bit is set to 1, reading BASE +15
results in the status of the Master Interrupt Status Register.
Register Address
(Base+)
Read/
Write
7
6
5
4
3
2
1
0
DATA_LO
8
R/W
LOW ORDER DATA BYTE
DATA-BIT 7
DATA-BIT 6
DATA-BIT 5
DATA-BIT 4
DATA-BIT 3
DATA-BIT 2
DATA-BIT 1
DATA-BIT 0
READBACK
(1)
8
R
LOW ORDER DATA BYTE
DATA-BIT 7
DATA-BIT 6
DATA-BIT 5
DATA-BIT 4
DATA-BIT 3
DATA-BIT 2
DATA-BIT 1
DATA-BIT 0
DATA_HI
9
R/W
HIGH ORDER DATA BYTE
DATA-BIT 15 DATA-BIT 14 DATA-BIT 13 DATA-BIT 12 DATA-BIT 11 DATA-BIT 10 DATA-BIT 9
DATA-BIT 8
READBACK
(1)
9
R
HIGH ORDER DATA BYTE
DATA-BIT 15 DATA-BIT 14 DATA-BIT 13 DATA-BIT 12 DATA-BIT 11 DATA-BIT 10 DATA-BIT 9
DATA-BIT 8
COMMAND
(2)
10
R/W
COMMAND
CMD-BIT 7
CMD-BIT 6
CMD-BIT 5
CMD-BIT 4
CMD-BIT 3
CMD-BIT 2
CMD-BIT 1
CMD-BIT 0
RESOURCE
(3)
10
R/W
DON’T CARE
INTERRUPT ROUTING ASSIGNMENT
IRQ[15-3] 0, 1, 2, 8, AND 13 NOT AVAILABLE
X
X
X
X
BIT 3
BIT 2
BIT 1
BIT 0
RESOURCE
ENABLE
11
W
X
X
X
READBACK
ENABLE
REGISTER
SELECT
X
X
INTERRUPT
ENABLE (4)
STATUS
11
R
DATA READY
X
X
INTERRUPT
REQUEST
PENDING (4)
REGISTER
SELECT
STATUS
X
X
INTERRUPT
ENABLE BIT
STATUS (4)
