2.7.2
Channel 2 - SAE J1708
2.8
Parallel Port I/O Address Selection
The par al lel port on the PCM- DSPIO can be I/O mapped at ei ther of 2 base ad dresses as
de ter mined by jumper block J10. The fol low ing il lus tra tion shows the J10 jump er ing for
each of the two sup ported ad dresses.
Page 2-8
PCM-DSPIO/J1708 OPERATIONS MANUAL
981117
WinSystems - "The Embedded Systems Authority"
U1 - Not Installed
U3 - Installed
U4 - Not Installed
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J2
J3
CH2 DB9
Jumper Positions
Driver IC Status
I/O Connector Pin Defs
N/C
TX/RX+
TX/RX-
N/C
GND
TX/RX+
TX/RX-
N/C
N/C
1 o
2 o
3 o
1 o
2 o
3 o
R2
R3
R4
TX/RX+
TX/RX-
R8
R1
4.7K
4.7K
4.7 OHM
4.7 OHM
C7 .0022 ufd
C3 .0022 ufd
Absent
1 o o 2
1 o o 2
J8
J10
Parallel Port Configuration
Jumpers J8, J10
vcc