W91550DN SERIES
Publication Release Date: November 1997
- 31 -
Revision A3
BONDING PAD DIAGRAM
31
30
33
32
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
(0, 0)
52
53
54
55
56
57
58
59
60
61
62
63
64
Notes:
1. The substrate must be connected to V
SS
.
2. The chip size is 3010.00
×
3060.00
µ
m
2
Unit:
µ
m
PAD
NO.
PAD
NAME
X
Y
PAD
NO.
PAD
NAME
X
Y
1
KMUTE
-1234.60
1369.20
17
5C
-1359.60
-1127.00
2
COM3
-1374.60
1322.70
18
6A
-1359.60
-1281.50
3
1A
-1359.60
1052.80
19
6B
-1117.60
-1384.60
4
1B
-1359.60
905.20
20
6C
-970.00
-1384.60
5
1C
-1359.60
741.40
21
7A
-811.00
-1384.60
6
2A
-1359.60
593.80
22
7B
-658.60
-1384.60
7
2B
-1359.60
430.00
23
7C
-494.80
-1384.60
8
2C
-1359.60
282.40
24
8A
-342.40
-1384.60
9
3A
-1359.60
118.60
25
8B
-183.40
-1384.60
10
3B
-1359.60
-29.00
26
S/
M
-28.90
-1384.60
11
3C
-1359.60
-192.80
27
8C
128. 00
-1384.60
12
4A
-1359.60
-340.40
28
9A
280.40
-1384.60
13
4B
-1359.60
-504.20
29
9B
439.40
-1384.60
14
4C
-1359.60
-651.80
30
9C
587.00
-1384.60
15
5A
-1359.60
-810.80
31
10A
746.00
-1384.60
16
5B
-1359.60
-963.20
32
10B
898.40
-1384.60