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Preliminary W77E516

Publication Release Date: August 16, 2002

- 19 - Revision A1

P4.1 Base Address High Byte Register

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: P41AH Address: 97h

Serial Port Control

Bit:

7

6

5

4

3

2

1

0

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

Mnemonic: SCON Address: 98h

SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines

whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When
used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually
cleared in software to clear the FE condition.

SM1: Serial port Mode bit 1:

SM0 SM1 Mode Description Length Baud rate

0 0 0 Synchronous 8 4/12 Tclk

0 1 1 Asynchronous 10 Variable

1 0 2 Asynchronous 11 64/32 Tclk

1 1 3 Asynchronous 11 Variable

SM2: Multiple processors communication. Setting this bit to 1 enables the multiprocessor

communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be
activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be
activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port
clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives
compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the
oscillator clock. This results in faster synchronous serial communication.

REN: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.

TB8: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software

as desired.

RB8: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit

that was received. In mode 0 it has no function.

TI: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or

at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.

RI: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or

halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2 apply to this bit. This bit can be cleared only by software.

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Summary of Contents for W77E516

Page 1: ...terrupts 8 Data Pointers 8 Power Management 8 On chip Data SRAM 8 7 MEMORY ORGANIZATION 8 Program Memory 8 Data Memory 9 Special Function Registers 10 Special Function Registers 11 Instruction 34 Instruction Timing 41 Power Management 49 Reset Conditions 51 Reset State 52 Interrupts 53 8 PROGRAMMABLE TIMERS COUNTERS 56 Timer Counters 0 1 56 Time base Selection 57 Timer Counter 2 59 Watchdog Timer ...

Page 2: ...rech Memory Cycles 75 12 TIMING WAVEFORMS 76 Program Memory Read Cycle 76 Data Memory Read Cycle 77 Data Memory Write Cycle 77 13 TYPICAL APPLICATION CIRCUITS 78 Expanded External Program Memory and Crystal 78 Expanded External Data Memory and Oscillator 79 14 PACKAGE DIMENSIONS 79 40 pin DIP 79 44 pin PLCC 80 44 pin QFP 80 15 APPLICATION NOTE 81 In system Programming Software Examples 81 ...

Page 3: ... In System Programmable ISP 64 KB Flash EPROM 4KB auxiliary Flash EPROM for loader program operating voltage from 4 5V to 5 5V on chip 1 KB MOVX SRAM three power saving modes 2 FEATURES 8 bit CMOS microcontroller High speed architecture of 4 clocks machine cycle runs up to 40 MHz Pin compatible with standard 80C52 Instruction set compatible with MCS 51 64KB on chip Mask ROM Four 8 bit I O Ports On...

Page 4: ...15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 INT3 P1 5 INT4 P1 6 INT5 P1 7 RST RXD P3 0 P4 3 TXD P3 1 INT0 P3 2 INT1 P3 3 T0 P3 4 T1 P3 5 X T A L 1 V S S P 2 4 A 1 2 P 2 3 A 1 1 P 2 2 A 1 0 P 2 1 A 9 P 2 0 A 8 X T A L 2 P 3 7 R D P 3 6 W R 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA P4 1 ALE PSEN P2 7 A15 P2 6 A14 P2 5 A13 28 27 26 25 24 23 22 21 20 19...

Page 5: ...P1 7 I O PORT 1 Port 1 is a bi directional I O port with internal pull ups The bits have alternate functions which are described below T2 P1 0 Timer Counter 2 external count input T2EX P1 1 Timer Counter 2 Reload Capture Direction control RXD1 P1 2 Serial port 1 RXD TXD1 P1 3 Serial port 1 TXD INT2 P1 4 External Interrupt 2 INT3 P1 5 External Interrupt 3 INT4 P1 6 External Interrupt 4 INT5 P1 7 Ex...

Page 6: ... XTAL2 Oscillator Interrupt PSW Instruction Decoder Sequencer Reset Block Bus lock Controller SFR RAM Address Power control Power monitor 256 bytes RAM SFR Stack Pointer B Addr Reg Incrementor PC Temp Reg DPTR 1 T2 Register T1 Register ACC Port 3 Latch Port 3 P0 0 Port 2 Latch Port 2 P2 0 Timer 2 1KB SRAM DPTR Watchdog Timer Port 4 Latch Port 4 P4 0 P4 3 64KB ROM ...

Page 7: ... This naturally speeds up the execution of instructions Consequently the W77E516 can run at a higher speed as compared to the original 8052 even if the same crystal is used Since the W77E516 is a fully static CMOS design it can also be operated at a lower crystal clock giving the same throughput in terms of instruction execution yet reducing the power consumption The 4 clocks per machine cycle fea...

Page 8: ...DLE and POWER DOWN modes of operation The W77E516 provides a new Economy mode that allow user to switch the internal clock rate divided by 4 64 or 1024 In the IDLE mode the clock to the CPU core is stopped while the timers serial ports and interrupts clock continue to operate In the POWER DOWN mode the entire clock is stopped and the chip operation is completely stopped This is the lowest power co...

Page 9: ...d FFFFH goes to the expanded bus on Port 0 and 2 This is the default condition In addition the W77E516 has the standard 256 bytes of on chip Scratchpad RAM This can be accessed either by direct addressing or by indirect addressing There are also some Special Function Registers SFRs which can only be accessed by direct addressing Since the Scratchpad RAM is only 256 bytes it can be used only when d...

Page 10: ... 64 65 66 67 58 59 5A 5B 5C 50 51 52 53 54 5D 5E 5F 55 56 57 48 49 4A 4B 4C 4D 4E 4F 40 41 42 43 44 45 46 47 38 39 3A 3B 3C 3D 3E 3F 30 31 32 33 34 35 36 37 28 29 2A 2B 2C 2D 2E 2F 20 21 22 23 24 25 26 27 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 Indirect RAM Direct RAM Bank 3 Bank 2 Bank 1 Bank 0 Figure 2 Scratchpad RAM Register Addressing Bit...

Page 11: ...e been added In some cases unused bits in the original 8052 have been given new functions The list of SFRs is as follows The table is condensed with eight locations per row Empty locations indicate that there are no registers at these addresses When a bit or register is not implemented it will read high Table 1 Special Function Register Location Table F8 EIP F0 B E8 EIE E0 ACC D8 WDCON D0 PSW C8 T...

Page 12: ... DPL 6 DPL 5 DPL 4 DPL 3 DPL 2 DPL 1 DPL 0 Mnemonic DPL Address 82h This is the low byte of the standard 8052 16 bit data pointer Data Pointer High Bit 7 6 5 4 3 2 1 0 DPH 7 DPH 6 DPH 5 DPH 4 DPH 3 DPH 2 DPH 1 DPH 0 Mnemonic DPH Address 83h This is the high byte of the standard 8052 16 bit data pointer Data Pointer Low1 Bit 7 6 5 4 3 2 1 0 DPL1 7 DPL1 6 DPL1 5 DPL1 4 DPL1 3 DPL1 2 DPL1 1 DPL1 0 Mn...

Page 13: ...DPL DPH will be selected DPS 1 7 These bits are reserved but will read 0 Power Control Bit 7 6 5 4 3 2 1 0 SM0D SMOD0 GF1 GF0 PD IDL Mnemonic PCON Address 87h SMOD This bit doubles the serial port baud rate in mode 1 2 and 3 when set to 1 SMOD0 Framing Error Detection Enable When SMOD0 is set to 1 then SCON 7 SCON1 7 indicates a Frame Error and acts as the FE FE_1 flag When SMOD0 is 0 then SCON 7 ...

Page 14: ... if the interrupt was edge triggered Otherwise it follows the pin IT1 Interrupt 1 type control Set cleared by software to specify falling edge low level triggered external inputs IE0 Interrupt 0 edge detect Set by hardware when an edge level is detected on INT0 This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered Otherwise it follows the ...

Page 15: ... by Timer 1 control bits Timer 1 Timer counter is stopped Timer 0 LSB Bit 7 6 5 4 3 2 1 0 TL0 7 TL0 6 TL0 5 TL0 4 TL0 3 TL0 2 TL0 1 TL0 0 Mnemonic TL0 Address 8Ah TL0 7 0 Timer 0 LSB Timer 1 LSB Bit 7 6 5 4 3 2 1 0 TL1 7 TL1 6 TL1 5 TL1 4 TL1 3 TL1 2 TL1 1 TL1 0 Mnemonic TL1 Address 8Bh TL1 7 0 Timer 1 LSB Timer 0 MSB Bit 7 6 5 4 3 2 1 0 TH0 7 TH0 6 TH0 5 TH0 4 TH0 3 TH0 2 TH0 1 TH0 0 Mnemonic TH0...

Page 16: ...k select When T0M is set to 1 timer 0 uses a divide by 4 clock and when set to 0 it uses a divide by 12 clock MD2 0 Stretch MOVX select bits These three bits are used to select the stretch value for the MOVXinstruction Using a variable MOVX length enables the user to access slower external memorydevices or peripherals without the need for external circuits The RD or WR strobe will be stretched by ...

Page 17: ...it P1 4 INT2 External Interrupt 2 P1 5 INT3 External Interrupt 3 P1 6 INT4 External Interrupt 4 P1 7 INT5 External Interrupt 5 External Interrupt Flag Bit 7 6 5 4 3 2 1 0 IE5 IE4 IE3 IE2 Mnemonic EXIF Address 91h IE5 External Interrupt 5 flag Set by hardware when a falling edge is detected on INT5 IE4 External Interrupt 4 flag Set by hardware when a rising edge is detected on INT4 IE3 External Int...

Page 18: ... P4xC0 Port 4 Chip select Mode address comparison 00 Compare the full address 16 bits length with the base address registers P4xAH and P4xAL 01 Compare the 15 high bits A15 A1 of address bus with the base address registers P4xAH and P4xAL 10 Compare the 14 high bits A15 A2 of address bus with the base address registers P4xAH and P4xAL 11 Compare the 8 high bits A15 A8 of address bus with the base ...

Page 19: ... mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 the SM2 bit controls the serial port clock If set to 0 then the serial port runs at a divide by 12 clock of the oscillator This gives compatibility with the standard 8052 When set to 1 the serial clock become divide by 4 of the oscillator clock This results in faster synchronous serial communication REN R...

Page 20: ...emonic P42AL Address 9Ah P4 2 Base Address High Byte Register Bit 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 Mnemonic P42AH Address 9Bh P4 3 Base Address Low Byte Register Bit 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 Mnemonic P43AL Address 9Ch P4 3 Base Address High Byte Register Bit 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 Mnemonic P43AH Address 9Dh ISP Control Register Bit 7 6 5 4 3 2 1 0...

Page 21: ... this bit to disable ISP mode device get back to normal operation including IDLE state Port 2 Bit 7 6 5 4 3 2 1 0 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 Mnemonic P2 Address A0h P2 7 0 Port 2 is a bi directional I O port with internal pull ups This port also provides the upper address bits for accesses to external memory Port 4 Chip Select Polarity Bit 7 6 5 4 3 2 1 0 P43INV P42INV P42INV P40INV P...

Page 22: ... designated Slave Address 1 Bit 7 6 5 4 3 2 1 0 Mnemonic SADDR1 Address AAh SADDR1 The SADDR1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated ISP Address Low Byte Bit 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 Mnemonic SFRAL Address ACh Low byte destination address for In System Programming operations SFRAH and SFRAL address a specif...

Page 23: ...B LDROM 0 1 1 0 0010 X X Erase 64K APROM 0 0 1 0 0010 X X Program 4KB LDROM 0 1 1 0 0001 Address in Data in Program 64KB APROM 0 0 1 0 0001 Address in Data in Read 4KB LDROM 0 1 0 0 0000 Address in Data out Read 64KB APROM 0 0 0 0 0000 Address in Data out Port 3 Bit 7 6 5 4 3 2 1 0 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Mnemonic P3 Address B0h P3 7 0 General purpose I O port Each pin also has an ...

Page 24: ...s B9h SADEN This register enables the Automatic Address Recognition feature of the Serial port 0 When a bit in the SADEN is set to 1 the same bit location in SADDR will be compared with the incoming serial data When SADEN n is 0 then the bit becomes a don t care in the comparison This register enables the Automatic Address Recognition feature of the Serial port 0 When all the bits of SADEN are 0 i...

Page 25: ...s results in faster synchronous serial communication REN_1 Receive enable When set to 1 serial reception is enabled otherwise reception is disabled TB8_1 This is the 9th bit to be transmitted in modes 2 and 3 This bit is set and cleared by software as desired RB8_1 In modes 2 and 3 this is the received 9th data bit In mode 1 if SM2_1 0 RB8_1 is the stop bit that was received In mode 0 it has no fu...

Page 26: ...4 to 4 clocks machine cycle and then from 4 to 1024 clocks machine cycle CD1 CD0 Clocks machine Cycle 0 0 Reserved 0 1 4 1 0 64 1 1 1024 SWB Switchback Enable Setting this bit allows an enabled external interrupt or serial port activity to force the CD1 CD0 to divide by 4 state 0 1 The device will switch modes at the start of the jump to interrupt service routine while a external interrupt is enab...

Page 27: ...o 1 and SWB 1 SPRA1 Serial Port 1 Receive Activity This bit is set during serial port 1 is currently receiving a data It is cleared when RI_1 bit is set by hardware Changing the Clock Divide Control bits CD0 CD1 will be ignored when this bit is set to 1 and SWB 1 SPTA0 Serial Port 0 Transmit Activity This bit is set during serial port 0 is currently transmitting data It is cleared when TI bit is s...

Page 28: ... Receive Clock Flag This bit determines the serial port 0 time base when receiving data in serial modes 1 or 3 If it is 0 then timer 1 overflow is used for baud rate generation otherwise timer 2 overflow is used Setting this bit forces timer 2 in baud rate generator mode TCLK Transmit Clock Flag This bit determines the serial port 0 time base when transmitting data in modes 1 and 3 If it is set to...

Page 29: ...ag Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine HC3 Hardware Clear INT2 flag Setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine T2CR Timer 2 Capture Reset In the Timer 2 Capture Mode this bit enables disables har...

Page 30: ...nic TH2 Address CDh TH2 Timer 2 MSB NVM Control Bit 7 6 5 4 3 2 1 0 ENVM EWR ETM3 ETM2 ETM1 ETM0 BUSY Mnemonic NVMCON Address CEh ENVM Enable 64 bytes NVM data cells while user would like to write or read NVM If user would not like to access NVM bytes Clear ENVM bit to reduce power consumption EWR Set this bit to write NVM bytes ETM3 ETM2 ETM1 ETM0 Adjust EEPROM timing for different MXT frequency ...

Page 31: ...d write content via this register CPU will decode DCID5 0 bits to address specific NVM byte User must set EWR bit before write to these NVM bytes If user set lock bit of security register by external programmer 64 bytes NVM will be protected Program Status Word Bit 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Mnemonic PSW Address D0h CY Carry flag Set for an arithmetic operation which results in a car...

Page 32: ...clear it manually A power fail reset will also clear the bit This bit helps software in determining the cause of a reset If EWT 0 the watchdog timer will have no affect on this bit EWT Enable Watchdog timer Reset Setting this bit will enable the Watchdog timer Reset function RWT Reset Watchdog Timer This bit helps in putting the watchdog timer into a know state It also helps in resetting the watch...

Page 33: ...pt 4 Enable EX3 External Interrupt 3 Enable EX2 External Interrupt 2 Enable B Register Bit 7 6 5 4 3 2 1 0 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 Mnemonic B Address F0h B 7 0 The B register is the standard 8052 register that serves as a second accumulator Extended Interrupt Priority Bit 7 6 5 4 3 2 1 0 PWDI PX5 PX4 PX3 PX2 Mnemonic EIP Address F8h EIP 7 5 Reserved bits PWDI Watchdog timer interrupt prior...

Page 34: ...of operands that the instruction has In case of jumps and calls there will be an additional cycle that will be needed to calculate the new address But overall the W77E516 reduces the number of dummy fetches and wasted cycles thereby improving efficiency as compared to the standard 8032 Table 2 Instructions that affect Flag settings Instruction Carry Overflow Auxiliary Carry Instruction Carry Overf...

Page 35: ...12 3 ADDC A R5 3D 1 1 4 12 3 ADDC A R6 3E 1 1 4 12 3 ADDC A R7 3F 1 1 4 12 3 ADDC A R0 36 1 1 4 12 3 ADDC A R1 37 1 1 4 12 3 ADDC A direct 35 2 2 8 12 1 5 ADDC A data 34 2 2 8 12 1 5 ACALL addr11 71 91 B1 11 31 51 D1 F1 2 3 12 24 2 AJMP ADDR11 01 21 41 61 81 A1 C1 E1 2 3 12 24 2 ANL A R0 58 1 1 4 12 3 ANL A R1 59 1 1 4 12 3 ANL A R2 5A 1 1 4 12 3 ANL A R3 5B 1 1 4 12 3 ANL A R4 5C 1 1 4 12 3 ANL A...

Page 36: ...ata rel BD 3 4 16 24 1 5 CJNE R6 data rel BE 3 4 16 24 1 5 CJNE R7 data rel BF 3 4 16 24 1 5 CLR A E4 1 1 4 12 3 CPL A F4 1 1 4 12 3 CLR C C3 1 1 4 12 3 CLR bit C2 2 2 8 12 1 5 CPL C B3 1 1 4 12 3 CPL bit B2 2 2 8 12 1 5 DEC A 14 1 1 4 12 3 DEC R0 18 1 1 4 12 3 DEC R1 19 1 1 4 12 3 DEC R2 1A 1 1 4 12 3 DEC R3 1B 1 1 4 12 3 DEC R4 1C 1 1 4 12 3 DEC R5 1D 1 1 4 12 3 DEC R6 1E 1 1 4 12 3 DEC R7 1F 1 ...

Page 37: ... 4 12 3 INC R5 0D 1 1 4 12 3 INC R6 0E 1 1 4 12 3 INC R7 0F 1 1 4 12 3 INC R0 06 1 1 4 12 3 INC R1 07 1 1 4 12 3 INC direct 05 2 2 8 12 1 5 INC DPTR A3 1 2 8 24 3 JMP A DPTR 73 1 2 8 24 3 JZ rel 60 2 3 12 24 2 JNZ rel 70 2 3 12 24 2 JC rel 40 2 3 12 24 2 JNC rel 50 2 3 12 24 2 JB bit rel 20 3 4 16 24 1 5 JNB bit rel 30 3 4 16 24 1 5 JBC bit rel 10 3 4 16 24 1 5 LCALL addr16 12 3 4 16 24 1 5 LJMP a...

Page 38: ...ect AA 2 2 8 12 1 5 MOV R3 direct AB 2 2 8 12 1 5 MOV R4 direct AC 2 2 8 12 1 5 MOV R5 direct AD 2 2 8 12 1 5 MOV R6 direct AE 2 2 8 12 1 5 MOV R7 direct AF 2 2 8 12 1 5 MOV R0 data 78 2 2 8 12 1 5 MOV R1 data 79 2 2 8 12 1 5 MOV R2 data 7A 2 2 8 12 1 5 MOV R3 data 7B 2 2 8 12 1 5 MOV R4 data 7C 2 2 8 12 1 5 MOV R5 data 7D 2 2 8 12 1 5 MOV R6 data 7E 2 2 8 12 1 5 MOV R7 data 7F 2 2 8 12 1 5 MOV R0...

Page 39: ...3 MOVC A A PC 83 1 2 8 24 3 MOVX A R0 E2 1 2 9 8 36 24 3 0 66 MOVX A R1 E3 1 2 9 8 36 24 3 0 66 MOVX A DPTR E0 1 2 9 8 36 24 3 0 66 MOVX R0 A F2 1 2 9 8 36 24 3 0 66 MOVX R1 A F3 1 2 9 8 36 24 3 0 66 MOVX DPTR A F0 1 2 9 8 36 24 3 0 66 MOV C bit A2 2 2 8 12 1 5 MOV bit C 92 2 2 8 24 3 ORL A R0 48 1 1 4 12 3 ORL A R1 49 1 1 4 12 3 ORL A R2 4A 1 1 4 12 3 ORL A R3 4B 1 1 4 12 3 ORL A R4 4C 1 1 4 12 3...

Page 40: ...3 SUBB A R2 9A 1 1 4 12 3 SUBB A R3 9B 1 1 4 12 3 SUBB A R4 9C 1 1 4 12 3 SUBB A R5 9D 1 1 4 12 3 SUBB A R6 9E 1 1 4 12 3 SUBB A R7 9F 1 1 4 12 3 SUBB A R0 96 1 1 4 12 3 SUBB A R1 97 1 1 4 12 3 SUBB A direct 95 2 2 8 12 1 5 SUBB A data 94 2 2 8 12 1 5 XCH A R0 C8 1 1 4 12 3 XCH A R1 C9 1 1 4 12 3 XCH A R2 CA 1 1 4 12 3 XCH A R3 CB 1 1 4 12 3 XCH A R4 CC 1 1 4 12 3 XCH A R5 CD 1 1 4 12 3 XCH A R6 C...

Page 41: ...ost of the instructions the number of machine cycles needed to execute the instruction is equal to the number of bytes in the instruction Of the 256 available op codes 128 of them are single cycle instructions Thus more than half of all op codes in the W77E516 are executed in just four clock periods Most of the two cycle instructions are those that have two byte instruction codes However there are...

Page 42: ...2 C1 OP CODE Address A15 8 Address A15 8 ALE PSEN PC AD7 0 PORT 2 CLK Operand Fetch C4 C3 C2 C1 OPERAND PC 1 Figure 4 Two Cycle Instruction Timing OPERAND OPERAND A7 0 A7 0 A7 0 OP CODE Address A15 8 Address A15 8 Address A15 8 Operand Fetch Operand Fetch Instruction Fetch C2 C3 C4 C2 C3 C4 C4 C3 C2 C1 C1 C1 CLK ALE PSEN AD7 0 PORT 2 Figure 5 Three Cycle Instruction Timing ...

Page 43: ...2 C1 C4 C3 C2 C1 CLK ALE PSEN AD7 0 Port 2 C4 C3 C2 C1 C4 C3 C2 C1 C4 C3 Figure 6 Four Cycle Instruction Timing OPERAND OPERAND OPERAND OP CODE Address A15 8 Address A15 8 Address A15 8 Address A15 8 A7 0 A7 0 A7 0 A7 0 Operand Fetch Operand Fetch Operand Fetch Operand Fetch Instruction Fetch C2 C1 C4 C3 C2 C1 CLK ALE PSEN AD7 0 PORT 2 C4 C3 C2 C1 C4 C3 C2 C1 C4 C3 C2 C1 C4 C3 OPERAND A7 0 Address...

Page 44: ...do this is by the INC instruction The advantage of having two Data Pointers is most obvious while performing block move operations The accompanying code shows how the use of two separate Data Pointers speeds up the execution time for code performing the same task Block Move with single Data Pointer SH and SL are the high and low bytes of Source Address DH and DL are the high and low bytes of Desti...

Page 45: ...OP Check if all done 3 Machine cycles in W77E516 12 15 CNT If CNT 50 Clock cycles in W77E516 12 15 50 4 12 750 4 3048 We can see that in the first program the standard 8032 takes 15720 cycles while the W77E516 takes only 5240 cycles for the same code In the second program written for the W77E516 program execution requires only 3048 clock cycles If the size of the block is increased then the saving...

Page 46: ...le Stretch Values M2 M1 M0 Machine Cycles RD or WR strobe width in Clocks RD or WR strobe width 25 MHz RD or WR strobe width 40 MHz 0 0 0 2 2 80 nS 50 nS 0 0 1 3 default 4 160 nS 100 nS 0 1 0 4 8 320 nS 200 nS 0 1 1 5 12 480 nS 300 nS 1 0 0 6 16 640 nS 400 nS 1 0 1 7 20 800 nS 500 nS 1 1 0 8 24 960 nS 600 nS 1 1 1 9 28 1120 nS 700 nS Next Instruction Machine Cycle Second Machine cycle First Machin...

Page 47: ...s MOVX Data out MOVX Data Address MOVX Inst Address MOVX Inst C4 C3 C2 C1 Figure 9 Dada Memory Write with Stretch Value 1 Next Instruction Machine Cycle Fourth Machine Cycle Third Machine Cycle Second Machine Cycle First Machine Cycle Last Cycle of Previous Instruction C4 PORT 2 PORT 0 WR PSEN ALE CLK C3 C2 D0 D7 A0 A7 D0 D7 A0 A7 D0 D7 A0 A7 D0 D7 A15 A8 A15 A8 A15 A8 A15 A8 A0 A7 C1 C4 C3 C2 C1 ...

Page 48: ...ll be inserted into next cycle The inserted wait state cycles are unlimited so the MOVX instruction cycle will end in which the wait state control signal is deactivated Using wait state control signal allows a dynamically access timimg to a selected external peripheral The WS bit is accessed by the Timed Access TA register Protection procedure Wait State Control Signal Timing when Stretch 1 C2 C3 ...

Page 49: ...eset pin has to be held high for at least two machine cycles I e 8 clock periods to be recognized as a valid reset In the reset condition the program counter is reset to 0000h and all the SFRs are set to the reset condition Since the clock is already running there is no delay and execution starts immediately In the Idle mode the Watchdog timer continues to run and if enabled a time out will cause ...

Page 50: ...ission or qualified external interrupt which is enabled and acknowledged without block conditions will cause CPU to return to divide by 4 mode For the serial port reception a switchback is generated by a falling edge associated with start bit if the serial port reception is enabled When a serial port transmission an instruction which writes a byte of data to serial port buffer will cause a switchb...

Page 51: ...the source of reset The user can use these flags to determine the cause of reset using software There are three ways of putting the device into reset state They are External reset Power on reset and Watchdog reset External Reset The device continuously samples the RST pin at state C4 of every machine cycle Therefore the RST pin must be held for at least 2 machine cycles to ensure detection of a va...

Page 52: ...are lost After a reset most SFRs are cleared Interrupts and Timers are disabled The Watchdog timer is disabled if the reset source was a POR The port SFRs have FFh written into them which puts the port pins in a high state Port 0 floats as it does not have on chip pull ups Table 6 SFR Reset Value SFR NAME RESET VALUE SFR NAME RESET VALUE P0 11111111b IE 00000000b SP 00000111b SADDR 00000000b DPL 0...

Page 53: ...rrupt is serviced The IEx flag will not be cleared by the hardware on entering the service routine If the interrupt continues to be held low even after the service routine is completed then the processor may acknowledge another interrupt request from the same source Note that the external interrupts INT2 to INT5 are edge triggered only By default the individual interrupt flag corresponding to exte...

Page 54: ...E1 3 Timer 1 Overflow TF1 4 Serial Port RI TI 5 Timer 2 Overflow TF2 EXF2 6 Serial Port 1 RI_1 TI_1 7 External Interrupt 2 IE2 8 External Interrupt 3 IE3 9 External Interrupt 4 IE4 10 External Interrupt 5 IE5 11 Watchdog Timer WDIF 12 lowest The interrupt flags are sampled every machine cycle In the same machine cycle the sampled interrupts are polled and their priority is resolved If certain cond...

Page 55: ...instruction is executed On execution of the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the stack The user must take care that the status of the stack is restored to what is was after the hardware LCALL if the execution is to return to the interrupted program The processor does not notice anything if the stack contents are modified and will procee...

Page 56: ...bit register Similarly Timer Counter 1 has two 8 bit registers TH1 and TL1 The two can be configured to operate either as timers counting machine cycles or as counters counting external inputs When configured as a Timer the timer counts clock cycles The timer clock can be programmed to be thought of as 1 12 of the system clock or 1 4 of the system clock In the Counter mode the register is incremen...

Page 57: ...e upper 3 bits of TLx are ignored The negative edge of the clock increments the count in the TLx register When the fifth bit in TLx moves from 1 to 0 then the count in the THx register is incremented When the count in THx moves from FFh to 00h then the overflow flag TFx in TCON SFR is set The counted input is enabled only if TRx is set and either GATE 0 or INTx 1 When C T is set to 0 then it will ...

Page 58: ... and 1 mode 2 allows counting of either clock cycles clock 12 or clock 4 or pulses on pin Tn 1 4 1 12 T0M CKCON 3 T1M CKCON 4 C T TMOD 2 C T TMOD 6 Interrupt T0 P3 4 T1 P3 5 TH0 TH1 TL0 TL1 TF0 TF1 TR0 TCON 4 TR1 TCON 6 GATE TMOD 3 GATE TMOD 7 INT0 P3 2 INT1 P3 3 7 0 TFx 7 0 Timer 1 functions are shown in brackets 1 0 0 1 Clock Source Mode input div by 4 osc 1 div by 64 osc 16 div by 1024 osc 256 ...

Page 59: ... capture reload capability As with the Timer 0 and Timer 1 counters there exists considerable flexibility in selecting and controlling the clock and in defining the operating mode The clock source for Timer Counter 2 may be selected for either the external T2 pin C T2 1 or the crystal oscillator which is divided by 12 or 4 C T2 0 The clock is then enabled when TR2 is a 1 and disabled when TR2 is a...

Page 60: ...aring the CP RL2 bit in the T2CON register and clearing the DCEN bit in T2MOD register In this mode Timer Counter 2 is a 16 bit up counter When the counter rolls over from FFFFh a reload is generated that causes the contents of the RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers The reload action also sets the TF2 bit If the EXEN2 bit is set then a negative transition of ...

Page 61: ... T T2CON 1 1 4 1 12 T2M CKCON 5 Down Counting Reload Value T2CON 7 Up Counting Reload Value T2 P1 0 T2CON 6 TR2 T2CON 2 T2EX P1 1 EXF2 Timer 2 Interrupt TF2 TH2 TL2 RCAP2H RCAP2L 1 0 0 1 0FFh 0FFh DCEN 1 Clock Source Mode input div by 4 osc 1 div by 64 osc 16 div by 1024 osc 256 Figure 16 16 Bit Auto reload Up Down Counter Baud Rate Generator Mode The baud rate generator mode is enabled by setting...

Page 62: ...c 2 div by 64 osc 32 div by 1024 osc 512 1 2 Figure 18 Programmable Clock Out Mode Watchdog Timer The Watchdog timer is a free running timer which can be programmed by the user to serve as a system monitor a time base generator or an event timer It is basically a set of dividers that divide the system clock The divider output is selectable and determines the time out interval When the time out occ...

Page 63: ...ence the processor may begin to execute errant code If this is left unchecked the entire system may crash Using the watchdog timer interrupt during software development will allow the user to select ideal watchdog reset locations The code is first written without the watchdog interrupt or reset Then the watchdog interrupt is enabled to identify code locations where interrupt occurs The user can no...

Page 64: ...antly it makes it highly improbable that errant code can enable or disable the watchdog timer Serial Port Serial port in the W77E516 is a full duplex port The W77E516 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition The serial ports are capable of synchronous as well as asynchronous communication In Synchronous mode the W77E516 gene...

Page 65: ...LOAD SBUF RX START RX SHIFT CLOCK SIN 4 12 1 0 SM2 Clock Source Mode input div by 4 osc 1 div by 64 osc 16 div by 1024 osc 256 Figure 20 Serial Port Mode 0 The TI flag is set high in C1 following the end of transmission of the last bit The serial port will receive data when REN is 1 and RI is zero The shift clock TxD will be activated and the serial port will latch data on the rising edge of shift...

Page 66: ...RxD pin is not 0 then this indicates an invalid start bit and the reception is immediately aborted The serial port again looks for a falling edge in the RxD line If a valid start bit is detected then the rest of the bits are also detected and shifted into the SBUF After shifting in 8 data bits there is one more shift to do after which the SBUF and RB8 are loaded and RI is set However certain condi...

Page 67: ... detector continuously monitors the RxD line sampling it at the rate of 16 times the selected baud rate When a falling edge is detected the divide by 16 counter is immediately reset This helps to align the bit boundaries with the rollovers of the divide by 16 counter The 16 states of the counter effectively divide the bit time into 16 slices The bit detection is done on a best of three basis The b...

Page 68: ... Serial Port Interrupt SMOD SMOD_1 SAMPLE Write to SBUF TX START SOUT T 0 1 TI PARIN STOP START LOAD CLOCK Read SBUF TX CLOCK RI SERIAL CONTROLLER RX CLOCK LOAD SBUF RX START RX SHIFT 2 16 1 TO 0 DETECTOR BIT DETECTOR 16 CLOCK SIN D8 TB8 Clock Source Mode input div by 4 osc 2 div by 64 osc 32 div by 1024 osc 512 Figure 22 Serial Port Mode 2 ...

Page 69: ...other modes by the incoming start bit if REN 1 The external device will start the communication by transmitting the start bit Table 10 Serial Ports Modes SM1 SM0 MODE TYPE BAUD CLOCK FRAME SIZE START BIT STOP BIT 9TH BIT FUNCTION 0 0 0 Synch 4 or 12 TCLKs 8 bits No No None 0 1 1 Asynch Timer 1 or 2 10 bits 1 1 None 1 0 2 Asynch 32 or 64 TCLKs 11 bits 1 1 0 1 1 1 3 Asynch Timer 1 or 2 11 bits 1 1 0...

Page 70: ...ress with the 9th bit set high When the master processor wants to transmit a block of data to one of the slaves it first sends out the address of the targeted slave or slaves All the slave processors should have their SM2 bit set high when waiting for an address byte This ensures that they will be interrupted only by the reception of a address byte The Automatic address recognition feature ensures...

Page 71: ...abled 9 TIMED ACCESS PROTECTION The W77E516 has several new features like the Watchdog timer on chip ROM size adjustment wait state control signal and Power on fail reset flag which are crucial to proper operation of the system If left unprotected errant code may write to the Watchdog control bits resulting in incorrect operation and loss of control In order to prevent this the W77E516 has a prote...

Page 72: ...the writing to the protected bit occurs after the window has closed and so there is effectively no change in the status of the protected bit In Example 4 the second write to TA occurs 4 machine cycles after the first write therefore the timed access window in not opened at all and the write to the protected bit fails 10 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITION RATING UNIT DC Power Suppl...

Page 73: ... Voltage P0 P1 P2 P3 EA VIL1 0 0 8 V VDD 4 5V Input Low Voltage RST 1 VIL2 0 0 8 V VDD 4 5V Input Low Voltage XTAL1 3 VIL3 0 0 8 V VDD 4 5V Input High Voltage P0 P1 P2 P3 EA VIH1 2 4 VDD 0 2 V VDD 5 5V Input High Voltage RST VIH2 3 5 VDD 0 2 V VDD 5 5V Input High Voltage XTAL1 3 VIH3 3 5 VDD 0 2 V VDD 5 5V Output Low Voltage P1 P2 P3 VOL1 0 45 V VDD 4 5V IOL 4 mA Output Low Voltage P0 ALE PSEN 2 V...

Page 74: ...CLCL 5 nS Address Hold After ALE Low tLLAX1 0 5 tCLCL 5 nS Address Hold After ALE Low for MOVX Write tLLAX2 0 5 tCLCL 5 nS ALE Low to Valid Instruction In tLLIV 2 5 tCLCL 20 nS ALE Low to PSEN Low tLLPL 0 5 tCLCL 5 nS PSEN Pulse Width tPLPH 2 0 tCLCL 5 nS PSEN Low to Valid Instruction In tPLIV 2 0 tCLCL 20 nS Input Instruction Hold After PSEN tPXIX 0 nS Input Instruction Float After PSEN tPXIZ tCL...

Page 75: ...MCS 2tCLCL 40 nS tMCS 0 tMCS 0 Port 0 Address to Valid Data In tAVDV1 3 0 tCLCL 20 2 0tCLCL 5 nS tMCS 0 tMCS 0 Port 2 Address to Valid Data In tAVDV2 3 5 tCLCL 20 2 5 tCLCL 5 nS tMCS 0 tMCS 0 ALE Low to RD or WR Low tLLWL 0 5 tCLCL 5 1 5 tCLCL 5 0 5 tCLCL 5 1 5 tCLCL 5 nS tMCS 0 tMCS 0 Port 0 Address to RD or WR Low tAVWL tCLCL 5 2 0 tCLCL 5 nS tMCS 0 tMCS 0 Port 2 Address to RD or WR Low tAVWL2 1...

Page 76: ...lity with the original 8051 family this device specifies the same parameter for each device using the same symbols The explanation of the symbols is as follows t Time A Address C Clock D Input Data H Logic level high L Logic level low I Instruction P PSEN Q Output Data R RD signal V Valid W WR signal X No longer a valid state Z Tri state 12 TIMING WAVEFORMS Program Memory Read Cycle tLLAX1 tPXIZ t...

Page 77: ...L1 tLLAX1 tWHLH tRLDV tRLRH tRLAZ tRHDZ tRHDX tAVDV2 tAVDV1 tLLWL ADDRESS A8 A15 ADDRESS A0 A7 INSTRUCTION IN DATA IN ADDRESS A0 A7 PORT 2 PORT 0 PSEN RD ALE tLLDV Data Memory Write Cycle tAVLL tAVWL1 tLLAX2 tWHLH tWLWH tQVWX tWHQX tAVDV2 tLLWL ADDRESS A8 A15 ADDRESS A0 A7 INSTRUCTION IN DATA OUT ADDRESS A0 A7 PORT 2 PORT 0 PSEN WR ALE ...

Page 78: ... 2 3 P1 3 4 P1 4 5 P1 5 6 P1 6 7 P1 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 WR P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 RD 16 PSEN 29 ALE 30 TXD 11 RXD 10 W77E516 10 u 8 2 K CC CRYSTAL C1 C2 R AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND A1 A2 A3 A4 A5 A6 A7 A1 A2 A3 A4 A5 A6 A7 A8 A9 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A10 A11 A12 A1...

Page 79: ...A8 A9 A10 A11 A12 A13 A14 CE GND A8 A9 A10 A11 A12 A13 A14 GND 22 27 OE WR 20256 V CC V Figure B 14 PACKAGE DIMENSIONS 40 pin DIP Seating Plane 1 Dimension D Max S include mold flash or tie bar burrs 2 Dimension E1 does not include interlead flash 3 Dimension D E1 include mold mismatch and are determined at the mold parting line 6 General appearance spec should be based on final visual inspection ...

Page 80: ...0 559 0 356 16 71 16 00 17 78 2 794 0 10 BSC 16 71 16 59 16 46 0 658 0 653 0 648 16 00 15 49 14 99 0 630 0 610 0 590 17 78 17 53 17 27 0 700 0 690 0 680 θ 44 pin QFP Seating Plane 11 22 12 See Detail F e b A y 1 A A L L 1 c E E H 1 D 44 H D 34 33 Detail F 1 Dimension D E do not include interlead flash 2 Dimension b does not include dambar protrusion intrusion 3 Controlling dimension Millimeter 4 G...

Page 81: ...nal SRAM buffer or through other interfaces to update the 64KB APROM EXAMPLE 1 Example of 64K APROM program Program will scan the P1 0 if P1 0 0 enters in system programming mode for updating the content of APROM code else executes the current ROM code XTAL 24 MHz chip 8052 RAMCHK OFF symbols CHPCON EQU 9FH TA EQU C7H SFRAL EQU ACH SFRAH EQU ADH SFRFD EQU AEH SFRCN EQU AFH ORG 0H LJMP 100H JUMP TO...

Page 82: ... mode 64KB APROM program depending user s application NORMAL_MODE User s application program EXAMPLE 2 Example of 4KB LDROM program This loader program will erase the 64KB APROM first then reads the new code from external SRAM and program them into 64KB APROM bank XTAL 24 MHz chip 8052 RAMCHK OFF symbols CHPCON EQU 9FH TA EQU C7H SFRAL EQU ACH SFRAH EQU ADH SFRFD EQU AEH SFRCN EQU AFH ORG 000H LJM...

Page 83: ...SET WAKE UP TIME FOR ERASE OPERATION ABOUT 15 mS DEPENDING ON USER S SYSTEM CLOCK RATE MOV R7 8AH MOV TL0 R6 MOV TH0 R7 ERASE_P_4K MOV SFRCN 22H SFRCN 22H ERASE 64K APROM0 SFRCN A2H ERASE 64K APROM1 MOV TCON 10H TCON 10H TR0 1 GO MOV PCON 01H ENTER IDLE MODE FOR ERASE OPERATION BLANK CHECK MOV SFRCN 0H SFRCN 00H READ 64KB APROM0 SFRCN 80H READ 64KB APROM1 MOV SFRAH 0H START ADDRESS 0H MOV SFRAL 0H...

Page 84: ...SAVE DATA INTO SRAM TO VERIFY CODE MOV SFRFD A SFRFD DATA IN MOV TCON 10H TCON 10H TR0 1 GO MOV PCON 01H ENTER IDLE MODE PRORGAMMING INC DPTR INC R2 CJNE R2 0H PROG_D_64K INC R1 MOV SFRAH R1 CJNE R1 0H PROG_D_64K VERIFY 64KB APROM BANK MOV R4 03H ERROR COUNTER MOV R6 FDH SET TIMER FOR READ VERIFY ABOUT 1 5 µS MOV R7 FFH MOV TL0 R6 MOV TH0 R7 MOV DPTR 0H The start address of sample code MOV R2 0H T...

Page 85: ...2 8751 3579 Winbond Electronics Corporation America 2727 North First Street San Jose CA 95134 U S A TEL 1 408 9436666 FAX 1 408 5441798 Winbond Electronics H K Ltd No 378 Kwun Tong Rd Kowloon Hong Kong FAX 852 27552064 Unit 9 15 22F Millennium City TEL 852 27513100 Please note that all data and specifications are subject to change without notice All the trade marks of products and companies mentio...

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